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61 lines
1.6 KiB
61 lines
1.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_until is
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port (
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clk : in std_logic
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);
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end entity psl_until;
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architecture psl of psl_until is
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signal a, b, c : std_logic;
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signal d, e, f : std_logic;
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signal g, h, i : std_logic;
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begin
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-- 01234567890
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SEQ_A : sequencer generic map ("_-___-_____") port map (clk, a);
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SEQ_B : sequencer generic map ("__--__----_") port map (clk, b);
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SEQ_C : sequencer generic map ("____-_____-") port map (clk, c);
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-- 01234567890
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SEQ_D : sequencer generic map ("_-___-_____") port map (clk, d);
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SEQ_E : sequencer generic map ("__---_-----") port map (clk, e);
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SEQ_F : sequencer generic map ("____-_____-") port map (clk, f);
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-- 012345
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SEQ_G : sequencer generic map ("_-____") port map (clk, g);
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SEQ_H : sequencer generic map ("______") port map (clk, h);
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SEQ_I : sequencer generic map ("__-___") port map (clk, i);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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UNTIL_0_a : assert always (a -> next (b until c));
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-- This assertion holds
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UNTIL_1_a : assert always (d -> next (e until f));
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-- This assertion holds
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UNTIL_2_a : assert always (g -> next (h until i));
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-- This assertion doesn't hold at cycle 4
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UNTIL_3_a : assert always (a -> next (b until_ c));
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-- This assertion holds
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UNTIL_4_a : assert always (d -> next (e until_ f));
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-- This assertion doesn't hold at cycle 2
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UNTIL_5_a : assert always (g -> next (h until_ i));
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end architecture psl;
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