library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_non_len_matching_and is
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port (
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clk : in std_logic
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);
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end entity psl_sere_non_len_matching_and;
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architecture psl of psl_sere_non_len_matching_and is
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signal req, done0, done1, done2, ack : std_logic;
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begin
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-- 01234567890
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SEQ_REQ : sequencer generic map ("_-_________") port map (clk, req);
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SEQ_DONE0 : sequencer generic map ("______-____") port map (clk, done0);
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SEQ_DONE1 : sequencer generic map ("________-__") port map (clk, done1);
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SEQ_DONE2 : sequencer generic map ("____-______") port map (clk, done2);
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SEQ_ACK : sequencer generic map ("_________-_") port map (clk, ack);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Non length matching AND three SERE
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-- Each of done0, done1 & done2 has to hold a cycle after
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-- req holded. Transfer is ended by ack holding one cycle
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-- after last done holded
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-- This assertion holds
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SERE_0_a : assert always {req} |=> {{done0[->] & done1[->] & done2[->]}; ack};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 11);
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-- synthesis translate_on
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end architecture psl;
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