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42 lines
898 B
42 lines
898 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_onehot0 is
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port (
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clk : in std_logic
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);
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end entity psl_onehot0;
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architecture psl of psl_onehot0 is
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signal a, b : std_logic_vector(3 downto 0);
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begin
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-- 012345678901234567
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SEQ_A : hex_sequencer generic map ("000111222444888888") port map (clk, a);
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SEQ_B : hex_sequencer generic map ("000111222444888fff") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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ONEHOT0_0_a : assert always onehot0(a);
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-- This assertion fails at cycle 15
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ONEHOT0_1_a : assert always onehot0(b);
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 20);
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-- synthesis translate_on
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end architecture psl;
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