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68 lines
1.8 KiB
68 lines
1.8 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_stable is
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port (
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clk : in std_logic
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);
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end entity psl_stable;
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architecture psl of psl_stable is
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signal valid, ack, a : std_logic;
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signal b : std_logic_vector(3 downto 0);
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begin
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-- 0123456789
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SEQ_VALID : sequencer generic map ("_--__---__") port map (clk, valid);
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SEQ_ACK : sequencer generic map ("__-____-__") port map (clk, ack);
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SEQ_A : sequencer generic map ("_--_______") port map (clk, a);
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SEQ_B : hex_sequencer generic map ("0110066600") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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STABLE_0_a : assert always {not valid; valid} |=> (stable(a) until_ ack);
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-- This assertion holds
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STABLE_1_a : assert always rose(valid) -> next (stable(b) until_ ack);
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-- Workaround needed before stable() was implemented
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-- With VHDL glue logic generating the
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-- previous value of a and simple comparing the two values
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a_reg : block is
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signal a_prev : std_logic;
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signal b_prev : std_logic_vector(b'range);
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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a_prev <= a;
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b_prev <= b;
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end if;
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end process;
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STABLE_2_a : assert always {not valid; valid} |=> (a = a_prev until_ ack);
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STABLE_3_a : assert always {not valid; valid} |=> (b = b_prev until_ ack);
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end block a_reg;
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-- Check parts of a vector
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-- This assertion holds
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STABLE_4_a : assert always rose(valid) -> next (stable(b(1 downto 0)) until_ ack);
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 10);
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-- synthesis translate_on
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end architecture psl;
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