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60 lines
1.7 KiB
60 lines
1.7 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.pkg.all;
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entity psl_next_event_a is
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port (
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clk : in std_logic
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);
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end entity psl_next_event_a;
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architecture psl of psl_next_event_a is
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signal a, c : std_logic;
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signal b : std_logic_vector(3 downto 0);
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begin
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-- 012345678901234567890123
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SEQ_A : sequencer generic map ("_-______________-_______") port map (clk, a);
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SEQ_B : hex_sequencer generic map ("443334477444433355554555") port map (clk, b);
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SEQ_C : sequencer generic map ("_____-___---______--_--_") port map (clk, c);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Check for one possible value of b
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-- Both assertions hold (see ghdl/ghdl#2157)
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NEXT_EVENT_0_a : assert always ((a and b = x"4") -> next_event_a(c)[1 to 4](b = x"4"))
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report "NEXT_EVENT_0_a failed";
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NEXT_EVENT_1_a : assert always ((a and b = x"5") -> next_event_a(c)[1 to 4](b = x"5"))
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report "NEXT_EVENT_1_a failed";
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-- Check for all possible values of b
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-- Workaround for missing PSL forall in {i to j} statement
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-- This assertions should hold
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-- Assertions for i = 4 & i = 5 don't hold, assuming GHDL bug
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check_b : for i in 0 to 2**b'length-1 generate
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signal i_slv : std_logic_vector(b'range);
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begin
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i_slv <= std_logic_vector(to_unsigned(i, 4));
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NEXT_EVENT_a : assert always ((a and b = i_slv) -> next_event_a(c)[1 to 4](b = i_slv));
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end generate check_b;
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 24);
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-- synthesis translate_on
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end architecture psl;
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