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46 lines
1010 B
46 lines
1010 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_consecutive_repetition is
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port (
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clk : in std_logic
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);
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end entity psl_sere_consecutive_repetition;
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architecture psl of psl_sere_consecutive_repetition is
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signal a, b, c : std_logic;
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begin
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-- 012345678
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SEQ_A : sequencer generic map ("_-_______") port map (clk, a);
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SEQ_B : sequencer generic map ("__----___") port map (clk, b);
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SEQ_C : sequencer generic map ("______-__") port map (clk, c);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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SERE_0_a : assert always {a} |=> {b; b; b; b; c};
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-- This assertion holds
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SERE_1_a : assert always {a} |=> {b[*4]; c};
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-- This assertion holds
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SERE_2_a : assert always {a} |=> {b[*3 to 5]; c};
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-- This assertion holds
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SERE_3_a : assert always {a} |=> {b[*]; c};
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-- This assertion holds
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SERE_4_a : assert always {a} |=> {b[+]; c};
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end architecture psl;
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