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41 lines
688 B
41 lines
688 B
-- Simple sequencer to generate waveforms for 1 bit std_logic signals
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-- Inspired by SymbioticEDA's sva-demos seq module
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-- https://github.com/SymbioticEDA/sva-demos/blob/master/seq.sv
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library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity sequencer is
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generic (
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seq : string
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);
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port (
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clk : in std_logic;
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data : out std_logic
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);
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end entity sequencer;
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architecture rtl of sequencer is
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signal index : natural := seq'low;
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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if (index < seq'high) then
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index <= index + 1;
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end if;
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end if;
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end process;
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data <= to_bit(seq(index));
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end architecture rtl;
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