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28 lines
708 B
28 lines
708 B
vunit psl_vunit_vu (psl_vunit(beh)) {
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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gen_0 : if FORMAL = "SERE_0" or formal = "ALL" generate
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-- This assertion holds
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SERE_0_a : assert {a};
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end generate gen_0;
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gen_1 : if FORMAL = "SERE_1" or formal = "ALL" generate
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-- This assertion holds
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SERE_1_a : assert {a; a};
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end generate gen_1;
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gen_2 : if FORMAL = "SERE_2" or formal = "ALL" generate
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-- This assertion holds
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SERE_2_a : assert {a; a and b};
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end generate gen_2;
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gen_3 : if FORMAL = "SERE_3" or formal = "ALL" generate
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-- This assertion doesn't hold at cycle 2
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SERE_3_a : assert always {a; a};
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end generate gen_3;
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}
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