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Various projects using Raspberry Pi
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raspberrypi/raspiFpga/syn/constraints/RaspiFpga.lpf

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update constraint file to new design
10 years ago
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  1. BLOCK RESETPATHS;
  2. BLOCK ASYNCPATHS;
  3. 

  4. BANK 0 VCCIO 3.3 V;
  5. BANK 2 VCCIO 3.3 V;
  6. BANK 1 VCCIO 3.3 V;
  7. BANK 3 VCCIO 3.3 V;
  8. 

  9. IOBUF ALLPORTS IO_TYPE=LVCMOS33;
  10. 

  11. LOCATE COMP "RaspiIrq_o" SITE "11";
  12. LOCATE COMP "SpiSte_i" 	 SITE "3";
  13. 

  14. IOBUF PORT "RaspiIrq_o" IO_TYPE=LVCMOS33 PULLMODE=NONE;
  15. 

  16. FREQUENCY NET "s_sys_clk" 26.600000 MHz;
  17. 

  18. SYSCONFIG SDM_PORT=PROGRAMN  I2C_PORT=DISABLE  SLAVE_SPI_PORT=ENABLE MCCLK_FREQ=26.6;