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tmeissner
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raspberrypi
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5 Commits (0e2170a504916d70df236ba9e1e4fe5454452ce1)
Author
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T. Meissner
0e2170a504
add Fibonacci RNG and control unit; using register
#0
as control/status and register
#1
as data register for the RNG instance
10 years ago
T. Meissner
943d8ca18d
add clearing of SPIIRQ register
10 years ago
T. Meissner
a39d535248
add change of s_spi_frame to NOP after write/read cycle and no new preamble was received
10 years ago
T. Meissner
0614c3eefd
Complete rework of RaspiFpgaCtrlE unit;
Set width of address and data to fixed value of 8 instead of generic ones
10 years ago
T. Meissner
ea35b8b595
add central control component of raspiFpga design
10 years ago