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247 lines
7.7 KiB
247 lines
7.7 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity RaspiFpgaCtrlE is
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port (
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--+ System if
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Rst_n_i : in std_logic;
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Clk_i : in std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector(7 downto 0);
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LocalData_i : in std_logic_vector(7 downto 0);
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LocalData_o : out std_logic_vector(7 downto 0);
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LocalAck_i : in std_logic;
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LocalError_i : in std_logic;
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--+ EFB if
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EfbSpiIrq_i : in std_logic;
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--+ RNG if
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RngStart_o : out std_logic;
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RngWait_o : out std_logic_vector(7 downto 0);
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RngRun_o : out std_logic_vector(7 downto 0);
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RngDataValid_i : in std_logic;
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RngData_i : in std_logic_vector(7 downto 0)
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);
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end entity RaspiFpgaCtrlE;
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architecture rtl of RaspiFpgaCtrlE is
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--+ EFB SPI slave register addresses
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constant C_SPICR0 : std_logic_vector(7 downto 0) := x"54"; --* ctrl reg 0
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constant C_SPICR1 : std_logic_vector(7 downto 0) := x"55"; --* ctrl reg 1
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constant C_SPICR2 : std_logic_vector(7 downto 0) := x"56"; --* ctrl reg 2
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constant C_SPIBR : std_logic_vector(7 downto 0) := x"57"; --* clk pre-scale
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constant C_SPICSR : std_logic_vector(7 downto 0) := x"58"; --* master chip select
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constant C_SPITXDR : std_logic_vector(7 downto 0) := x"59"; --* transmit data
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constant C_SPIISR : std_logic_vector(7 downto 0) := x"5A"; --* status
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constant C_SPIRXDR : std_logic_vector(7 downto 0) := x"5B"; --* receive data
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constant C_SPIIRQ : std_logic_vector(7 downto 0) := x"5C"; --* interrupt request
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constant C_SPIIRQEN : std_logic_vector(7 downto 0) := x"5D"; --* interrupt request enable
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--+ Register file addresses
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constant C_REG_RNGSTATUS : natural := 0;
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constant C_REG_RNGWAIT : natural := 1;
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constant C_REG_RNGRUN : natural := 2;
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constant C_REG_RNGDATA : natural := 3;
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type t_cmdctrl_fsm is (IDLE, INIT_SET, INIT_ACK, TXDR_SET, TXDR_ACK, INT_WAIT,
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RXDR_SET, RXDR_ACK, INT_CLEAR_SET, INT_CLEAR_ACK);
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signal s_cmdctrl_fsm : t_cmdctrl_fsm;
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type t_wb_master is record
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adr : std_logic_vector(7 downto 0);
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data : std_logic_vector(7 downto 0);
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end record t_wb_master;
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type t_wb_master_array is array (natural range <>) of t_wb_master;
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constant C_INIT : t_wb_master_array := ((C_SPICR1, x"80"),
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(C_SPICR2, x"00"),
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(C_SPIIRQEN, x"08"));
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signal s_init_cnt : natural range 0 to C_INIT'length;
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type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
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signal s_register : t_byte_array(0 to 127);
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signal s_register_we : std_logic;
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signal s_register_address : natural range s_register'range;
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type t_spi_frame is (NOP, HEADER, WRITE_DATA, READ_DATA);
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signal s_spi_frame : t_spi_frame;
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begin
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--+ FSM to write/request data from the wishbone master
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--+ Combinatoral outputs
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LocalWen_o <= '1' when s_cmdctrl_fsm = INIT_SET or s_cmdctrl_fsm = TXDR_SET or s_cmdctrl_fsm = INT_CLEAR_SET else '0';
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LocalRen_o <= '1' when s_cmdctrl_fsm = RXDR_SET else '0';
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LocalAdress_o <= C_INIT(s_init_cnt).adr when s_cmdctrl_fsm = INIT_SET else
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C_SPITXDR when s_cmdctrl_fsm = TXDR_SET else
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C_SPIRXDR when s_cmdctrl_fsm = RXDR_SET else
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C_SPIIRQ when s_cmdctrl_fsm = INT_CLEAR_SET else
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(others => '0');
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LocalData_o <= C_INIT(s_init_cnt).data when s_cmdctrl_fsm = INIT_SET else
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s_register(s_register_address) when s_cmdctrl_fsm = TXDR_SET and s_spi_frame = READ_DATA else
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x"FF";
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--+ FSM to write/request data from the wishbone master
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--+ State logic/register
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CmdCtrlP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Rst_n_i = '0') then
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s_cmdctrl_fsm <= IDLE;
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else
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FsmC : case s_cmdctrl_fsm is
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when IDLE =>
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s_cmdctrl_fsm <= INIT_SET;
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when INIT_SET =>
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s_cmdctrl_fsm <= INIT_ACK;
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when INIT_ACK =>
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if (LocalAck_i = '1') then
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if (s_init_cnt = C_INIT'length) then
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s_cmdctrl_fsm <= TXDR_SET;
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else
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s_cmdctrl_fsm <= INIT_SET;
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end if;
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end if;
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when TXDR_SET =>
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s_cmdctrl_fsm <= TXDR_ACK;
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when TXDR_ACK =>
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if (LocalAck_i = '1') then
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s_cmdctrl_fsm <= INT_WAIT;
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end if;
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when INT_WAIT =>
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if (EfbSpiIrq_i = '1') then
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s_cmdctrl_fsm <= RXDR_SET;
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end if;
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when RXDR_SET =>
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s_cmdctrl_fsm <= RXDR_ACK;
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when RXDR_ACK =>
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if (LocalAck_i = '1') then
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s_cmdctrl_fsm <= INT_CLEAR_SET;
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end if;
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when INT_CLEAR_SET =>
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s_cmdctrl_fsm <= INT_CLEAR_ACK;
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when INT_CLEAR_ACK =>
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if (LocalAck_i = '1') then
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s_cmdctrl_fsm <= TXDR_SET;
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end if;
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when others =>
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null;
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end case FsmC;
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end if;
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end if;
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end process CmdCtrlP;
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--+ FSM to write/request data from the wishbone master
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--+ Registered outputs
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CmdRegisterP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Rst_n_i = '0') then
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s_init_cnt <= 0;
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s_spi_frame <= NOP;
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s_register_address <= 0;
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else
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case s_cmdctrl_fsm is
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when IDLE =>
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s_init_cnt <= 0;
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s_spi_frame <= NOP;
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s_register_address <= 0;
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when INIT_SET =>
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s_init_cnt <= s_init_cnt + 1;
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when RXDR_ACK =>
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if (LocalAck_i = '1') then
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if (s_spi_frame = HEADER) then
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s_register_address <= to_integer(unsigned(LocalData_i(6 downto 0)));
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if (LocalData_i(7) = '0') then
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s_spi_frame <= READ_DATA;
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else
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s_spi_frame <= WRITE_DATA;
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end if;
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else
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if (LocalData_i = x"00") then
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s_spi_frame <= HEADER;
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else
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s_spi_frame <= NOP;
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end if;
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end if;
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end if;
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when others =>
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null;
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end case;
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end if;
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end if;
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end process CmdRegisterP;
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--+ Register bank write enable
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s_register_we <= LocalAck_i when s_cmdctrl_fsm = RXDR_ACK and s_spi_frame = WRITE_DATA else '0';
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--+ Register bank 127x8
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RegisterFileP : process (Clk_i) is
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begin
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if (rising_edge(Clk_i)) then
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if (Rst_n_i = '0') then
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s_register <= (others => (others => '0'));
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s_register(C_REG_RNGWAIT) <= x"0F";
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s_register(C_REG_RNGRUN) <= x"0F";
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else
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s_register(C_REG_RNGSTATUS)(0) <= '0'; -- reset RNG start after each clock cycle
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if (s_register_we = '1') then
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s_register(s_register_address) <= LocalData_i;
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end if;
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-- register RNG data
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if (RngDataValid_i = '1') then
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s_register(C_REG_RNGSTATUS)(1) <= '1';
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s_register(C_REG_RNGDATA) <= RngData_i;
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end if;
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-- clear RNG done flag when RNG was started
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if (s_register(C_REG_RNGSTATUS)(0) = '1') then
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s_register(C_REG_RNGSTATUS)(1) <= '0';
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end if;
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end if;
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end if;
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end process RegisterFileP;
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--+ RNG control outputs
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RngStart_o <= s_register(C_REG_RNGSTATUS)(0);
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RngWait_o <= s_register(C_REG_RNGWAIT);
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RngRun_o <= s_register(C_REG_RNGRUN);
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end architecture rtl;
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