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new folder 'cpld' with test project to test the CPLD on USB-AVR-CPLD

* sim/makefile with targets to simulate the cpld design
* sim/cpldtestt.vhd file with the testbench
* sim/cpldtestt.tcl file with control commands for gtkwave
* src/cpldteste.vhd file with test design (@ the moment a simple 10101 @ gpio port)
* syn/constraints/cpldtest.ucf with implementation constraints
* syn/makefile with targets to build the cpld design
T. Meissner 8 years ago
parent
commit
8c3ed041a9
5 changed files with 161 additions and 0 deletions
  1. 4
    0
      cpld/sim/cpldtestt.tcl
  2. 62
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      cpld/sim/cpldtestt.vhd
  3. 24
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      cpld/sim/makefile
  4. 37
    0
      cpld/src/cpldteste.vhd
  5. 34
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      cpld/syn/constraints/cpldtest.ucf

+ 4
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cpld/sim/cpldtestt.tcl View File

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+set signals [list]
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+lappend signals "top.cpldtestt.s_cpld_clk"
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+lappend signals "top.cpldtestt.s_cpld_gpio"
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+set num_added [ gtkwave::addSignalsFromList $signals ]

+ 62
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cpld/sim/cpldtestt.vhd View File

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+library ieee;
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+use ieee.std_logic_1164.all;
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+use ieee.numeric_std.all;
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+
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+
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+entity CpldTestT is
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+end entity CpldTestT;
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+
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+
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+architecture rtl of CpldTestT is
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+
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+
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+  component CpldTestE is
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+    port (
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+      -- globals
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+      XcClk_i    : in    std_logic;
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+      -- avr
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+      AvrData_io : inout std_logic_vector(13 downto 0);
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+      AvrSck_i   : in    std_logic;
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+      AvrMosi_i  : in    std_logic;
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+      AvrMiso_o  : out   std_logic;
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+      -- spi flash
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+      SpfRst_n_o : out   std_logic;
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+      SpfCs_n_o  : out   std_logic;
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+      SpfSck_o   : out   std_logic;
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+      SpfMosi_o  : out   std_logic;
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+      SpfMiso_i  : in    std_logic;
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+      -- gpio
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+      Gpio_io    : inout std_logic_vector(4 downto 0)
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+    );
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+  end component CpldTestE;
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+
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+  signal s_cpld_clk  : std_logic := '0';
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+  signal s_cpld_gpio : std_logic_vector(4 downto 0);
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+
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+begin
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+
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+
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+  s_cpld_clk <= not(s_cpld_clk) after 20 ns;
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+
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+  i_CpldTestE : CpldTestE
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+  port map
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+    (
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+      -- globals
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+      XcClk_i    => s_cpld_clk,
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+      -- avr
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+      AvrData_io => open,
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+      AvrSck_i   => '0',
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+      AvrMosi_i  => '0',
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+      AvrMiso_o  => open,
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+      -- spi flash
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+      SpfRst_n_o => open,
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+      SpfCs_n_o  => open,
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+      SpfSck_o   => open,
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+      SpfMosi_o  => open,
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+      SpfMiso_i  => '0',
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+      -- gpio
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+      Gpio_io    => s_cpld_gpio
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+    );
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+
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+
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+end architecture rtl;

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cpld/sim/makefile View File

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+PROJECT = cpldtestt
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+
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+MAKE_WORKDIR := $(shell mkdir -p work)
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+
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+WORKDIR = ${CURDIR}/work
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+
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+all : sim wave
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+
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+.PHONY:
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+sim : $(PROJECT).ghw
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+
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+
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+$(PROJECT).ghw : ../src/*.vhd $(PROJECT).vhd
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+	cd $(WORKDIR); ghdl -a ../../src/*.vhd ../$(PROJECT).vhd
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+	cd $(WORKDIR); ghdl -e $(PROJECT)
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+	cd $(WORKDIR); ghdl -r $(PROJECT) --wave=../$(PROJECT).ghw --assert-level=error --stop-time=150us
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+
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+wave : $(PROJECT).ghw $(PROJECT).tcl
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+	gtkwave -T $(PROJECT).tcl $(PROJECT).ghw
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+	
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+clean :
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+	echo "# cleaning simulation files"
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+	rm -f $(PROJECT).ghw
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+	rm -rf $(WORKDIR)

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cpld/src/cpldteste.vhd View File

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+library ieee;
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+  use ieee.std_logic_1164.all;
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+  use ieee.numeric_std.all;
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+
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+
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+entity CpldTestE is
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+  port (
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+    -- globals
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+    XcClk_i    : in    std_logic;
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+    -- avr
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+    AvrData_io : inout std_logic_vector(13 downto 0);
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+    AvrSck_i   : in    std_logic;
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+    AvrMosi_i  : in    std_logic;
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+    AvrMiso_o  : out   std_logic;
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+    -- spi flash
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+    SpfRst_n_o : out   std_logic;
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+    SpfCs_n_o  : out   std_logic;
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+    SpfSck_o   : out   std_logic;
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+    SpfMosi_o  : out   std_logic;
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+    SpfMiso_i  : in    std_logic;
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+    -- gpio
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+    Gpio_io    : inout std_logic_vector(4 downto 0)
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+  );
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+end entity CpldTestE;
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+
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+
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+architecture rtl of CpldTestE is
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+
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+
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+begin
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+
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+
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+  -- test gpio pins
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+  Gpio_io <= "10101";
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+
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+
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+end architecture rtl;

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cpld/syn/constraints/cpldtest.ucf View File

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+# pin locations
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+XcClk_i        LOC = PIN43; 
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+AvrData_io<0>  LOC = PIN6;
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+AvrData_io<1>  LOC = PIN5;
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+AvrData_io<2>  LOC = PIN3;
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+AvrData_io<3>  LOC = PIN34;
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+AvrData_io<4>  LOC = PIN33;
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+AvrData_io<5>  LOC = PIN32;
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+AvrData_io<6>  LOC = PIN31;
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+AvrData_io<7>  LOC = PIN30;
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+AvrData_io<8>  LOC = PIN29;
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+AvrData_io<9>  LOC = PIN28;
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+AvrData_io<10> LOC = PIN27;
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+AvrData_io<11> LOC = PIN23;
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+AvrData_io<12> LOC = PIN12;
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+AvrData_io<13> LOC = PIN8;
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+AvrData_io<14> LOC = PIN7;
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+AvrSck_i       LOC = PIN44;
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+AvrMosi_i      LOC = PIN2;
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+AvrMiso_o      LOC = PIN1;
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+SpfRst_n_o     LOC = PIN21;
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+SpfCs_n_o      LOC = PIN22;
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+SpfSck_o       LOC = PIN20;
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+SpfMosi_o      LOC = PIN13;
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+SpfMiso_i      LOC = PIN14;
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+Gpio_io<0>     LOC = PIN42;
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+Gpio_io<1>     LOC = PIN41;
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+Gpio_io<2>     LOC = PIN40;
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+Gpio_io<3>     LOC = PIN39;
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+Gpio_io<4>     LOC = PIN38;
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+
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+# clock timing
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+NET "XcClk_i" TNM_NET = XcClk_i;
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+TIMESPEC TS_Clk_i = PERIOD "XcClk_i" 40 ns HIGH 50%;