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46 lines
895 B
46 lines
895 B
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity CpldTestE is
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port (
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-- globals
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XcClk_i : in std_logic;
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-- avr
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AvrData_io : inout std_logic_vector(14 downto 0);
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AvrSck_i : in std_logic;
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AvrMosi_i : in std_logic;
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AvrMiso_o : out std_logic;
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-- spi flash
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SpfRst_n_o : out std_logic;
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SpfCs_n_o : out std_logic;
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SpfSck_o : out std_logic;
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SpfMosi_o : out std_logic;
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SpfMiso_i : in std_logic;
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-- gpio
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Gpio_io : inout std_logic_vector(4 downto 0)
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);
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end entity CpldTestE;
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architecture rtl of CpldTestE is
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begin
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-- test gpio pins
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process (XcClk_i) is
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begin
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if(rising_edge(XcClk_i)) then
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if(AvrData_io(0) = '0') then
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Gpio_io <= "00000";
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else
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Gpio_io <= "10101";
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end if;
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end if;
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end process;
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end architecture rtl;
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