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170 lines
4.7 KiB
170 lines
4.7 KiB
-- Simple wishbone verification IP
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-- For use with GHDL only
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-- Suitable for simulation & formal verification
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-- Copyright 2021 by Torsten Meissner (programming@goodcleanfun.de)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library wishbone;
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use wishbone.wishbone_pkg.all;
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entity wishbone_vip is
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generic (
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MODE : string := "CLASSIC";
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ASSERTS : boolean := true;
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COVERAGE : boolean := true
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);
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port (
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-- syscon signals
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WbSysCon : in t_wb_syscon;
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-- master signals
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WbMaster : in t_wb_master;
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-- slave signals
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WbSlave : in t_wb_slave
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);
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end entity wishbone_vip;
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architecture verification of wishbone_vip is
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function count_ones (data : in std_logic_vector) return natural is
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variable v_return : natural := 0;
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begin
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for i in data'range loop
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if (to_x01(data(i)) = '1') then
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v_return := v_return + 1;
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end if;
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end loop;
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return v_return;
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end function count_ones;
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function one_hot (data : in std_logic_vector) return boolean is
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begin
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return count_ones(data) = 1;
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end function one_hot;
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function one_hot_0 (data : in std_logic_vector) return boolean is
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begin
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return count_ones(data) <= 1;
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end function one_hot_0;
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alias Clk is WbSysCon.Clk;
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alias Reset is WbSysCon.Reset;
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signal s_wb_slave_resp : std_logic_vector(2 downto 0);
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begin
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s_wb_slave_resp <= WbSlave.Rty & WbSlave.Err & WbSlave.Ack;
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-- Static interface checks
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-- Always enabled, regardless of generic ASSERTS setting
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MODE_a : assert MODE = "CLASSIC"
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report "ERROR: Unsupported mode"
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severity failure;
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DATA_MS_WIDTH_a : assert WbMaster.Dat'length = 8 or WbMaster.Dat'length = 16 or
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WbMaster.Dat'length = 32 or WbMaster.Dat'length = 64
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report "ERROR: Invalid Master Data length"
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severity failure;
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DATA_SM_WIDTH_a : assert WbSlave.Dat'length = 8 or WbSlave.Dat'length = 16 or
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WbSlave.Dat'length = 32 or WbSlave.Dat'length = 64
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report "ERROR: Invalid Slave Data length"
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severity failure;
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DATA_EQUAL_WIDTH_a : assert WbMaster.Dat'length = WbSlave.Dat'length
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report "ERROR: Master & Slave Data don't have equal length"
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severity failure;
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default clock is rising_edge(Clk);
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ASSERTS_G : if ASSERTS generate
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signal s_wb_master : t_wb_master(Adr(WbMaster.Adr'range),
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Dat(WbMaster.Dat'range),
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Sel(WbMaster.Sel'range),
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Tgc(WbMaster.Tgc'range),
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Tga(WbMaster.Tga'range),
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Tgd(WbMaster.Tgd'range));
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signal s_wb_slave : t_wb_slave(Dat(WbSlave.Dat'range),
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Tgd(WbSlave.Tgd'range));
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begin
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-- Create copies of bus signals
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process (Clk) is
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begin
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if rising_edge(Clk) then
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s_wb_master <= WbMaster;
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s_wb_slave <= WbSlave;
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end if;
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end process;
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-- RULE 3.20
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STB_RESET_a : assert always Reset -> not WbMaster.Stb;
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CYC_RESET_a : assert always Reset -> not WbMaster.Cyc;
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-- RULE 3.25
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STB_CYC_a : assert always WbMaster.Stb -> WbMaster.Cyc;
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-- RULE 3.45
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ACK_ERR_RTY_ONEHOT_a : assert always one_hot_0(s_wb_slave_resp);
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-- RULE 3.50
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ACK_ERR_RTY_STB_a : assert always or s_wb_slave_resp -> WbMaster.Stb;
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DAT_STABLE_STB_a : assert always WbMaster.Stb and s_wb_slave_resp = "000" ->
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next (WbMaster.Dat = s_wb_master.Dat);
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end generate ASSERTS_G;
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COVERAGE_G : if COVERAGE generate
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sequence s_single_read (boolean resp) is {
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not WbMaster.Cyc;
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WbMaster.Cyc and not WbMaster.Stb[*];
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{s_wb_slave_resp = "000"[*]; resp} &&
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{WbMaster.Cyc and WbMaster.Stb and not WbMaster.We}[+]
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};
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sequence s_single_write (boolean resp) is {
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not WbMaster.Cyc;
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WbMaster.Cyc and not WbMaster.Stb[*];
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{s_wb_slave_resp = "000"[*]; resp} &&
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{WbMaster.Cyc and WbMaster.Stb and WbMaster.We}[+]
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};
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SINGLE_READ_ACKED_c : cover s_single_read(WbSlave.Ack)
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report "Single read with ack finished";
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SINGLE_READ_ERROR_c : cover s_single_read(WbSlave.Err)
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report "Single read with error finished";
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SINGLE_READ_RETRY_c : cover s_single_read(WbSlave.Rty)
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report "Single read with retry finished";
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SINGLE_WRITE_ACKED_c : cover s_single_write(WbSlave.Ack)
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report "Single read with ack finished";
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SINGLE_WRITE_ERROR_c : cover s_single_write(WbSlave.Err)
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report "Single read with error finished";
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SINGLE_WRITE_RETRY_c : cover s_single_write(WbSlave.Rty)
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report "Single read with retry finished";
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end generate COVERAGE_G;
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end architecture verification;
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