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161 lines
5.5 KiB
161 lines
5.5 KiB
-- Simple wishbone verification IP
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-- For use with GHDL only
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-- Suitable for simulation & formal verification
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-- Copyright 2021 by Torsten Meissner (programming@goodcleanfun.de)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package wishbone_pkg is
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type t_slv_array is array (natural range <>) of std_logic_vector;
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type t_wb_syscon is record
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Reset : std_logic;
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Clk : std_logic;
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end record;
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type t_wb_master is record
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Cyc : std_logic;
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Stb : std_logic;
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We : std_logic;
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Lock : std_logic;
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Adr : std_logic_vector;
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Dat : std_logic_vector;
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Sel : std_logic_vector;
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Tgc : std_logic_vector;
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Tga : std_logic_vector;
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Tgd : std_logic_vector;
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end record;
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type t_wb_slave is record
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Ack : std_logic;
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Err : std_logic;
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Rty : std_logic;
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Dat : std_logic_vector;
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Tgd : std_logic_vector;
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end record;
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function to_string(wb : t_wb_master) return string;
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function to_string(wb : t_wb_slave) return string;
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procedure log_wishbone (signal clk : std_logic; master : t_wb_master; slave : t_wb_slave);
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procedure cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in std_logic_vector;
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WDat : in std_logic_vector;
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RDat : out std_logic_vector);
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procedure single_cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in std_logic_vector;
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WDat : in std_logic_vector;
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RDat : out std_logic_vector);
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procedure block_cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in t_slv_array;
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WDat : in t_slv_array;
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RDat : out t_slv_array);
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end package wishbone_pkg;
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package body wishbone_pkg is
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procedure cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in std_logic_vector;
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WDat : in std_logic_vector;
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RDat : out std_logic_vector) is
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begin
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master.Cyc <= '1';
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master.Stb <= '1';
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master.We <= Wen;
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master.Adr <= Adr;
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master.Dat <= WDat;
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wait until rising_edge(syscon.Clk) and (slave.Ack or slave.Err or slave.Rty) = '1';
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RDat := slave.Dat;
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end procedure cycle;
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procedure single_cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in std_logic_vector;
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WDat : in std_logic_vector;
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RDat : out std_logic_vector) is
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begin
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cycle(syscon, master, slave, Wen, Adr, WDat, RDat);
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master.Cyc <= '0';
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master.Stb <= '0';
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master.We <= '0';
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master.Adr <= (master.Adr'range => '0');
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master.Dat <= (master.Dat'range => '0');
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wait until rising_edge(syscon.Clk);
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end procedure single_cycle;
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procedure block_cycle (signal syscon : in t_wb_syscon;
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signal master : out t_wb_master;
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signal slave : in t_wb_slave;
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Wen : in std_logic;
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Adr : in t_slv_array;
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WDat : in t_slv_array;
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RDat : out t_slv_array) is
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begin
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assert Adr'length = WDat'length and WDat'length = RDat'length;
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for i in Adr'low to Adr'high-1 loop
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cycle(syscon, master, slave, Wen, Adr(i), WDat(i), RDat(i));
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end loop;
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single_cycle(syscon, master, slave, Wen, Adr(Adr'high), WDat(WDat'high), RDat(RDat'high));
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end procedure block_cycle;
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function to_string(wb : t_wb_master) return string is
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begin
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return "Cyc: " & to_string(wb.Cyc) & LF &
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"Stb: " & to_string(wb.Stb) & LF &
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"We: " & to_string(wb.We) & LF &
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"Lock: " & to_string(wb.Lock) & LF &
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"Adr: " & to_hstring(wb.Adr) & LF &
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"Dat: " & to_hstring(wb.Dat) & LF &
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"Sel: " & to_hstring(wb.Sel) & LF &
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"Tgc: " & to_hstring(wb.Tgc) & LF &
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"Tga: " & to_hstring(wb.Tga) & LF &
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"Tgd: " & to_hstring(wb.Tgd);
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end function to_string;
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function to_string(wb : t_wb_slave) return string is
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begin
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return "Ack: " & to_string(wb.Ack) & LF &
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"Err: " & to_string(wb.Err) & LF &
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"Rty: " & to_string(wb.Rty) & LF &
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"Dat: " & to_hstring(wb.Dat) & LF &
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"Tgd: " & to_hstring(wb.Tgd);
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end function to_string;
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procedure log_wishbone (signal clk : std_logic; master : t_wb_master; slave : t_wb_slave) is
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begin
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wait until rising_edge(clk);
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report "Wishbone master:" & LF & to_string(master);
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report "Wishbone slave:" & LF & to_string(slave);
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end procedure log_wishbone;
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end package body wishbone_pkg;
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