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111 lines
3.2 KiB
111 lines
3.2 KiB
-- Simple wishbone verification IP
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-- For use with GHDL only
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-- Suitable for simulation & formal verification
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-- Copyright 2021 by Torsten Meissner (programming@goodcleanfun.de)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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library wishbone;
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use wishbone.wishbone_pkg.all;
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entity wishbone_tb is
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end entity wishbone_tb;
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architecture testbench of wishbone_tb is
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constant C_CLOCK_PERIOD : time := 2 ns;
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constant C_WB_ADDR_WIDTH : positive := 32;
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constant C_WB_DATA_WIDTH : positive := 32;
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constant C_WB_SEL_WIDTH : positive := 4;
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constant C_WB_TGA_WIDTH : positive := 4;
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constant C_WB_TGC_WIDTH : positive := 4;
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constant C_WB_TGD_WIDTH : positive := 4;
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signal s_wb_syscon : t_wb_syscon := ('1', '1');
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signal s_wb_master : t_wb_master(Adr(C_WB_ADDR_WIDTH-1 downto 0),
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Dat(C_WB_DATA_WIDTH-1 downto 0),
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Sel(C_WB_SEL_WIDTH-1 downto 0),
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Tgc(C_WB_TGC_WIDTH-1 downto 0),
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Tga(C_WB_TGA_WIDTH-1 downto 0),
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Tgd(C_WB_TGD_WIDTH-1 downto 0));
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signal s_wb_slave : t_wb_slave(Dat(C_WB_DATA_WIDTH-1 downto 0),
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Tgd(C_WB_TGD_WIDTH-1 downto 0));
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alias s_clk is s_wb_syscon.Clk;
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alias s_reset is s_wb_syscon.Reset;
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begin
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s_clk <= not s_clk after C_CLOCK_PERIOD / 2;
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s_reset <= '0' after 4 ns;
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wb_master_p : process is
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subtype t_wb_array is t_slv_array(0 to 7)(open);
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variable v_wb_adr : t_wb_array(open)(C_WB_ADDR_WIDTH-1 downto 0);
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variable v_wb_wdata : t_wb_array(open)(C_WB_DATA_WIDTH-1 downto 0);
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variable v_wb_rdata : t_wb_array(open)(C_WB_DATA_WIDTH-1 downto 0);
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begin
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s_wb_master.Cyc <= '0';
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s_wb_master.Stb <= '0';
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wait until s_reset = '0';
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-- single read cycles
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for wait_cycles in 0 to 3 loop
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single_cycle(s_wb_syscon, s_wb_master, s_wb_slave, '0', v_wb_adr(0), v_wb_wdata(0), v_wb_rdata(0));
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end loop;
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-- single write cycles
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for wait_cycles in 0 to 3 loop
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single_cycle(s_wb_syscon, s_wb_master, s_wb_slave, '1', v_wb_adr(0), v_wb_wdata(0), v_wb_rdata(0));
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end loop;
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-- block cycles
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block_cycle(s_wb_syscon, s_wb_master, s_wb_slave, '0', v_wb_adr, v_wb_wdata, v_wb_rdata);
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block_cycle(s_wb_syscon, s_wb_master, s_wb_slave, '1', v_wb_adr, v_wb_wdata, v_wb_rdata);
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wait for 10 ns;
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stop(0);
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end process wb_master_p;
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wb_slave_p : process is
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begin
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s_wb_slave.Rty <= '0';
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s_wb_slave.Err <= '0';
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s_wb_slave.Ack <= '0';
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wait until s_reset = '0';
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loop
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for wait_cycles in 0 to 3 loop
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wait until rising_edge(s_clk) and (s_wb_master.Cyc and s_wb_master.Stb) = '1';
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if wait_cycles /= 0 then
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wait for C_CLOCK_PERIOD * wait_cycles - 1 ps;
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wait until rising_edge(s_clk);
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end if;
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s_wb_slave.Ack <= '1';
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wait until rising_edge(s_clk);
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s_wb_slave.Ack <= '0';
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end loop;
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end loop;
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wait;
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end process wb_slave_p;
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i_wishbone_vip : entity wishbone.wishbone_vip
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generic map (
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MODE => "CLASSIC"
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)
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port map (
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WbSysCon => s_wb_syscon,
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WbMaster => s_wb_master,
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WbSlave => s_wb_slave
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);
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end testbench;
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