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105 lines
2.8 KiB
105 lines
2.8 KiB
-- Simple wishbone verification IP
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-- For use with GHDL only
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-- Suitable for simulation & formal verification
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-- Copyright 2021 by Torsten Meissner (programming@goodcleanfun.de)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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library wishbone;
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use wishbone.wishbone_pkg.all;
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entity wishbone_tb is
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end entity wishbone_tb;
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architecture testbench of wishbone_tb is
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constant C_WB_ADDR_WIDTH : positive := 32;
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constant C_WB_DATA_WIDTH : positive := 32;
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constant C_WB_SEL_WIDTH : positive := 4;
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constant C_WB_TGA_WIDTH : positive := 4;
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constant C_WB_TGC_WIDTH : positive := 4;
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constant C_WB_TGD_WIDTH : positive := 4;
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signal s_wb_syscon : t_wb_syscon := ('1', '1');
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signal s_wb_master : t_wb_master(Adr(C_WB_ADDR_WIDTH-1 downto 0),
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Dat(C_WB_DATA_WIDTH-1 downto 0),
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Sel(C_WB_SEL_WIDTH-1 downto 0),
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Tgc(C_WB_TGC_WIDTH-1 downto 0),
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Tga(C_WB_TGA_WIDTH-1 downto 0),
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Tgd(C_WB_TGD_WIDTH-1 downto 0));
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signal s_wb_slave : t_wb_slave(Dat(C_WB_DATA_WIDTH-1 downto 0),
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Tgd(C_WB_TGD_WIDTH-1 downto 0));
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signal s_wb_slave_resp : std_logic_vector(2 downto 0);
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alias s_clk is s_wb_syscon.Clk;
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alias s_reset is s_wb_syscon.Reset;
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begin
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s_clk <= not s_clk after 1 ns;
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s_reset <= '0' after 4 ns;
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s_wb_slave_resp <= s_wb_slave.Rty & s_wb_slave.Err & s_wb_slave.Ack;
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wb_master_p : process is
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begin
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s_wb_master.Cyc <= '0';
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s_wb_master.Stb <= '0';
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wait until s_reset = '0';
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-- simple reads
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for i in 0 to 2 loop
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wait until rising_edge(s_clk);
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s_wb_master.Cyc <= '1';
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s_wb_master.Stb <= '1';
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s_wb_master.We <= '0';
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wait until s_wb_slave_resp(i) = '1' and rising_edge(s_clk);
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report "Master: end simple read cycle";
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s_wb_master.Cyc <= '0';
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s_wb_master.Stb <= '0';
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end loop;
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wait for 10 ns;
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stop(0);
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end process wb_master_p;
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wb_slave_p : process is
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variable v_resp : std_logic_vector(2 downto 0) := "000";
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begin
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(s_wb_slave.Rty, s_wb_slave.Err, s_wb_slave.Ack) <= v_resp;
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wait until s_reset = '0';
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-- simple read
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for i in 0 to 2 loop
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wait until (s_wb_master.Cyc and s_wb_master.Stb) = '1' and rising_edge(s_clk);
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v_resp(i) := '1';
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(s_wb_slave.Rty, s_wb_slave.Err, s_wb_slave.Ack) <= v_resp;
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wait until not s_wb_master.Stb;
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v_resp(i) := '0';
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(s_wb_slave.Rty, s_wb_slave.Err, s_wb_slave.Ack) <= v_resp;
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end loop;
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wait;
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end process wb_slave_p;
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i_wishbone_vip : entity wishbone.wishbone_vip
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generic map (
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MODE => "CLASSIC"
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)
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port map (
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WbSysCon => s_wb_syscon,
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WbMaster => s_wb_master,
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WbSlave => s_wb_slave
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);
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end testbench;
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