Examples and design pattern for VHDL verification
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  1. .PHONY: sim compile clean wave
  2. sim \
  3. work/psl_test_endpoint \
  4. work/psl_test_endpoint.ghw: work/psl_test_endpoint.o log
  5. @echo Run test ...
  6. @cd work; ghdl -r --std=08 -fpsl psl_test_endpoint \
  7. --psl-report=../log/psl_test_endpoint.json \
  8. --wave=../log/psl_test_endpoint.ghw \
  9. --stop-time=200ns
  10. compile \
  11. work/psl_test_endpoint.o: psl_test_endpoint.vhd work
  12. @echo "Analyse & elaborate test ..."
  13. cd work; ghdl -a --std=08 -fpsl ../psl_test_endpoint.vhd
  14. cd work; ghdl -e --std=08 -fpsl psl_test_endpoint
  15. wave: work/psl_test_endpoint.ghw
  16. @echo Run waveform viewer ...
  17. @gtkwave log/psl_test_endpoint.ghw -S psl_test_endpoint.tcl &
  18. work \
  19. log:
  20. mkdir $@
  21. clean:
  22. @echo Remove generated files ...
  23. @rm -rf work log