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Adapt to new GHDL feature to make endpoints visible in VHDL

T. Meissner 3 years ago
parent
commit
7c1f4b1c4d
1 changed files with 7 additions and 17 deletions
  1. 7
    17
      psl_test_endpoint/psl_test_endpoint.vhd

+ 7
- 17
psl_test_endpoint/psl_test_endpoint.vhd View File

@@ -40,31 +40,21 @@ begin
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     s_write <= '0';
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     s_read  <= '0';
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     wait until rising_edge(s_clk);
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-    --stop(0);
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+    stop(0);
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     wait;
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   end process TestP;
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   -- psl default clock is rising_edge(s_clk);
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   -- psl endpoint E_TEST0 is {not(s_write); s_write};
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-  -- psl endpoint E_TEST1 is {s_write; s_write and not(s_read)};
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-  -- psl sequence abc_seq is {not(s_write); s_write};
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-  -- ASSERT0 should be passed, but not failed
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-  -- ASSERT1 should be failed
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-  -- ASSERT2 should not be passed
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-  -- psl ASSERT0 : assert always {E_TEST0} |=> {s_read} report  "ASSERT0";
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-  -- psl ASSERT1 : assert always {E_TEST0} |-> {s_read} report  "ASSERT1";
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-  -- psl ASSERT2 : assert always {E_TEST1} |-> {s_read} report  "ASSERT2";
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-
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-  -- COVERAGE0..COVERAGE2 should all hit @ same time
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-  -- COVERAGE3 should never hit
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-
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-  -- psl COVERAGE0 : cover {not(s_write); s_write} report "COVERED0";
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-  -- psl COVERAGE1 : cover {abc_seq} report "COVERED1";
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-  -- psl COVERAGE2 : cover {E_TEST0} report "COVERED2";
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-  -- psl COVERAGE3 : cover {E_TEST1} report "COVERED3";
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+  process is
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+  begin
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+    wait until E_TEST0;
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+    report "HIT";
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+    wait;
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+  end process;
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 end architecture test;