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# vhdl_verification |
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Examples and design pattern for VHDL verification. All examples run with GHDL, the open source VHDL simulator. |
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You have to use the latest version of GHDL, as the examples use features which where added to GHDL very recently. |
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### osvvm_fsm_coverage |
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Example to use OSVVMs CoveragePkg package to do FSM state coverage. State changes are used as BINS which are counted |
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in an object of type CovPType. The testbench accesses these state coverage data CoveragePkg procedures. So, the testbench |
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can react to the FSM coverage if necessary. Furthermore the state changes are checked by some PSL assertions. |
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### psl_endpoint_eval_in_vhdl |
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Example to show a recently feature added to GHDL which allows to evaluate PSL endpoints in VHDL code. It simply defines |
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an PSL endpoint and sets a boolean value dependent on the value of the PSL endpoint. |
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### psl_test_endpoint |
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This example was as test case to check the feature of evaluating PSL endpoints in VHDL, which was recently added to GHDL. |
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See GHDL issue [#45](https://github.com/tgingold/ghdl/issues/45) for details. |
