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Add writing psl endpoint value into VHDL boolean signal

T. Meissner 3 years ago
parent
commit
c48ea0f288
1 changed files with 13 additions and 1 deletions
  1. 13
    1
      psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd

+ 13
- 1
psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd View File

@@ -19,6 +19,7 @@ architecture test of psl_endpoint_eval_in_vhdl is
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   signal s_clk   : std_logic := '0';
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   signal s_write : std_logic;
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   signal s_read  : std_logic;
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+  signal s_test0 : boolean;
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 begin
@@ -59,4 +60,15 @@ begin
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   end process;
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-end architecture test;
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+  process is
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+  begin
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+    wait until rising_edge(s_clk);
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+    if (E_TEST0) then
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+      s_test0 <= true;
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+    else
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+      s_test0 <= false;
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+    end if;
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+  end process;
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+
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+
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+end architecture test;