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Add writing psl endpoint value into VHDL boolean signal

master
T. Meissner 5 years ago
parent
commit
c48ea0f288
1 changed files with 13 additions and 1 deletions
  1. +13
    -1
      psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd

+ 13
- 1
psl_endpoint_eval_in_vhdl/psl_endpoint_eval_in_vhdl.vhd View File

@ -19,6 +19,7 @@ architecture test of psl_endpoint_eval_in_vhdl is
signal s_clk : std_logic := '0';
signal s_write : std_logic;
signal s_read : std_logic;
signal s_test0 : boolean;
begin
@ -59,4 +60,15 @@ begin
end process;
end architecture test;
process is
begin
wait until rising_edge(s_clk);
if (E_TEST0) then
s_test0 <= true;
else
s_test0 <= false;
end if;
end process;
end architecture test;

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