Examples and design pattern for VHDL verification
vhdl
ghdl
osvvm
psl
fpga
testbenches
coverage

osvvm_fsm_coverage.tcl 225B

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  1. set signals [list]
  2. lappend signals "top.osvvm_fsm_coverage.s_reset_n"
  3. lappend signals "top.osvvm_fsm_coverage.s_clk"
  4. lappend signals "top.osvvm_fsm_coverage.s_fsm_state"
  5. set num_added [ gtkwave::addSignalsFromList $signals ]