tmeissner
/
cryptocores
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
187 Commits
1 Branch
1.7 MiB
Tree: 28b2cd3856
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '28b2cd3856'
${ noResults }
cryptocores/des/sim/verilog/tb_des.tcl

12 lines
394 B
Raw Normal View History

new verilog testbench, makefile & tcl-file
13 years ago
​
​
​
add acceptin & acceptout ports
10 years ago
new verilog testbench, makefile & tcl-file
13 years ago
​
​
​
add acceptin & acceptout ports
10 years ago
new verilog testbench, makefile & tcl-file
13 years ago
​
 
  1. set signals [list]
  2. lappend signals "tb_des.reset"
  3. lappend signals "tb_des.clk"
  4. lappend signals "tb_des.validin"
  5. lappend signals "tb_des.acceptout"
  6. lappend signals "tb_des.mode"
  7. lappend signals "tb_des.key"
  8. lappend signals "tb_des.datain"
  9. lappend signals "tb_des.validout"
  10. lappend signals "tb_des.acceptin"
  11. lappend signals "tb_des.dataout"
  12. set num_added [ gtkwave::addSignalsFromList $signals ]