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cryptography ip-cores in vhdl / verilog
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cryptocores/cbcmac_des/sim/verilog/tb_cbcmac_des.tcl

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add verilog simulation environment for cbcmac-des
9 years ago
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  1. set signals [list]
  2. lappend signals "tb_cbcmac_des.reset"
  3. lappend signals "tb_cbcmac_des.clk"
  4. lappend signals "tb_cbcmac_des.validin"
  5. lappend signals "tb_cbcmac_des.acceptout"
  6. lappend signals "tb_cbcmac_des.start"
  7. lappend signals "tb_cbcmac_des.key"
  8. lappend signals "tb_cbcmac_des.datain"
  9. lappend signals "tb_cbcmac_des.validout"
  10. lappend signals "tb_cbcmac_des.acceptin"
  11. lappend signals "tb_cbcmac_des.dataout"
  12. set num_added [ gtkwave::addSignalsFromList $signals ]