cryptography ip-cores in vhdl / verilog
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  1. // ======================================================================
  2. // DES encryption/decryption
  3. // algorithm according to FIPS 46-3 specification
  4. // Copyright (C) 2007 Torsten Meissner
  5. //-----------------------------------------------------------------------
  6. // This program is free software; you can redistribute it and/or modify
  7. // it under the terms of the GNU General Public License as published by
  8. // the Free Software Foundation; either version 2 of the License, or
  9. // (at your option) any later version.
  10. //
  11. // This program is distributed in the hope that it will be useful,
  12. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. // GNU General Public License for more details.
  15. //
  16. // You should have received a copy of the GNU General Public License
  17. // along with this program; if not, write to the Free Software
  18. // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. // ======================================================================
  20. module des
  21. (
  22. input reset_i, // async reset
  23. input clk_i, // clock
  24. input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
  25. input [0:63] key_i, // key input
  26. input [0:63] data_i, // data input
  27. input valid_i, // input key/data valid flag
  28. output [0:63] data_o, // data output
  29. output valid_o // output data valid flag
  30. );
  31. `include "des_pkg.v"
  32. reg [0:17] valid;
  33. reg [0:16] mode;
  34. wire valid_o = valid[17];
  35. always @(posedge clk_i, negedge reset_i) begin
  36. if(~reset_i) begin
  37. valid <= 0;
  38. end
  39. else begin
  40. // shift registers
  41. valid[1:17] <= valid[0:16];
  42. valid[0] <= valid_i;
  43. mode[1:16] <= mode[0:15];
  44. mode[0] <= mode_i;
  45. end
  46. end
  47. endmodule