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cryptocores
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cryptography ip-cores in vhdl / verilog
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Torsten Meissner 804a359af4 new synchronous process for mode & valid signals 13 years ago
aes new verily version of ads, startup code only at the moment 13 years ago
cbcdes remove OVL support in older, finished & verified projects 13 years ago
cbctdes remove OVL support in older, finished & verified projects 13 years ago
des new synchronous process for mode & valid signals 13 years ago
tdes remove OVL support in older, finished & verified projects 13 years ago