Browse Source

remove OVL support in older, finished & verified projects

master
Torsten Meissner 12 years ago
parent
commit
114a4e1072
6 changed files with 5 additions and 86 deletions
  1. +1
    -19
      cbcdes/sim/makefile
  2. +1
    -20
      cbctdes/sim/makefile
  3. +0
    -6
      des/rtl/des.vhd
  4. +1
    -1
      des/rtl/des_pkg.vhd
  5. +1
    -20
      des/sim/makefile
  6. +1
    -20
      tdes/sim/makefile

+ 1
- 19
cbcdes/sim/makefile View File

@ -19,29 +19,11 @@
# ======================================================================
# enable the compile of the OVL library
# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
OVL_ENABLE = 0
# the location and sources of the OVL library (copyright of Accellera)
# OVL is not included in this project, you can download it from
# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
OVL_LOC = ../../../../OVL/
ifeq ($(OVL_ENABLE), 1)
OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
$(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
$(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
$(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
else
OVL_SRC =
endif
all : sim wave
sim : tb_cbcdes.ghw
tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd $(OVL_SRC)
ghdl -a $(OVL_SRC)
tb_cbcdes.ghw : ../rtl/*.vhd tb_cbcdes.vhd
ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/cbcdes.vhd tb_cbcdes.vhd
ghdl -e tb_cbcdes
ghdl -r tb_cbcdes --wave=tb_cbcdes.ghw --assert-level=error --stop-time=220us


+ 1
- 20
cbctdes/sim/makefile View File

@ -19,30 +19,11 @@
# ======================================================================
# enable the compile of the OVL library
# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
OVL_ENABLE = 0
# the location and sources of the OVL library (copyright of Accellera)
# OVL is not included in this project, you can download it from
# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
OVL_LOC = ../../../../OVL/
ifeq ($(OVL_ENABLE), 1)
OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
$(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
$(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
$(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
else
OVL_SRC =
endif
all : sim wave
sim : tb_cbctdes.ghw
tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd $(OVL_SRC)
ghdl -a $(OVL_SRC)
tb_cbctdes.ghw : ../rtl/*.vhd tb_cbctdes.vhd
ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd ../rtl/cbctdes.vhd tb_cbctdes.vhd
ghdl -e tb_cbctdes
ghdl -r tb_cbctdes --wave=tb_cbctdes.ghw --assert-level=error --stop-time=45us


+ 0
- 6
des/rtl/des.vhd View File

@ -19,12 +19,6 @@
-- ======================================================================
-- Revision 1.0 2007/02/04
-- Initial release
-- Revision 1.1 2007/02/05
-- Corrected error in use of mode register for key calculation
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;


+ 1
- 1
des/rtl/des_pkg.vhd View File

@ -330,4 +330,4 @@ PACKAGE BODY des_pkg IS
END FUNCTION pc2;
END PACKAGE BODY des_pkg;
END PACKAGE BODY des_pkg;

+ 1
- 20
des/sim/makefile View File

@ -19,31 +19,12 @@
# ======================================================================
# enable the compile of the OVL library
# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
OVL_ENABLE = 0
# the location and sources of the OVL library (copyright of Accellera)
# OVL is not included in this project, you can download it from
# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
OVL_LOC = ../../../../OVL/
ifeq ($(OVL_ENABLE), 1)
OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
$(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
$(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
$(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
else
OVL_SRC =
endif
all : sim wave
sim : tb_des.ghw
tb_des.ghw : ../rtl/*.vhd tb_des.vhd $(OVL_SRC)
ghdl -a $(OVL_SRC)
tb_des.ghw : ../rtl/*.vhd tb_des.vhd
ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd tb_des.vhd
ghdl -e tb_des
ghdl -r tb_des --wave=tb_des.ghw --assert-level=error --stop-time=11us


+ 1
- 20
tdes/sim/makefile View File

@ -19,30 +19,11 @@
# ======================================================================
# enable the compile of the OVL library
# if set to 1, you must have the OVL_SRC files in the OVL_LOC directory
OVL_ENABLE = 0
# the location and sources of the OVL library (copyright of Accellera)
# OVL is not included in this project, you can download it from
# the Accellera homepage: http://www.accellera.org/downloads/standards/ovl/
OVL_LOC = ../../../../OVL/
ifeq ($(OVL_ENABLE), 1)
OVL_SRC = $(OVL_LOC)/std_ovl.vhd $(OVL_LOC)/std_ovl_components.vhd \
$(OVL_LOC)/std_ovl_procs.vhd $(OVL_LOC)/std_ovl_clock_gating.vhd \
$(OVL_LOC)/std_ovl_reset_gating.vhd $(OVL_LOC)/ovl_*.vhd \
$(OVL_LOC)/vhdl93/ovl_*_rtl.vhd
else
OVL_SRC =
endif
all : sim wave
sim : tb_tdes.ghw
tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd $(OVL_SRC)
ghdl -a $(OVL_SRC)
tb_tdes.ghw : ../rtl/*.vhd tb_tdes.vhd
ghdl -a ../rtl/des_pkg.vhd ../rtl/des.vhd ../rtl/tdes.vhd tb_tdes.vhd
ghdl -e tb_tdes
ghdl -r tb_tdes --wave=tb_tdes.ghw --assert-level=error --stop-time=45us


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