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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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54
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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Torsten Meissner
114a4e1072
remove OVL support in older, finished & verified projects
13 years ago
aes
you can now include the OVL library if you set the OVL_ENABLE flag to 1
13 years ago
cbcdes
remove OVL support in older, finished & verified projects
13 years ago
cbctdes
remove OVL support in older, finished & verified projects
13 years ago
des
remove OVL support in older, finished & verified projects
13 years ago
tdes
remove OVL support in older, finished & verified projects
13 years ago