cryptography ip-cores in vhdl / verilog
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  1. # ======================================================================
  2. # DES encryption/decryption
  3. # algorithm according to FIPS 46-3 specification
  4. # Copyright (C) 2020 Torsten Meissner
  5. #-----------------------------------------------------------------------
  6. # This program is free software; you can redistribute it and/or modify
  7. # it under the terms of the GNU General Public License as published by
  8. # the Free Software Foundation; either version 2 of the License, or
  9. # (at your option) any later version.
  10. # This program is distributed in the hope that it will be useful,
  11. # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. # GNU General Public License for more details.
  14. # You should have received a copy of the GNU General Public License
  15. # along with this program; if not, write to the Free Software
  16. # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. # ======================================================================
  18. DESIGN_NAME := des
  19. SRC_FILES := ../../../des/rtl/vhdl/$(DESIGN_NAME)_pkg.vhd ../../../des/rtl/vhdl/$(DESIGN_NAME).vhd
  20. VHD_STD := 08
  21. .PHONY: all
  22. all : $(DESIGN_NAME)_synth.vhd syn
  23. .PHONY: syn
  24. syn: $(DESIGN_NAME).json
  25. $(DESIGN_NAME).o: $(SRC_FILES)
  26. ghdl -a --std=$(VHD_STD) $(SRC_FILES)
  27. $(DESIGN_NAME)_synth.vhd: $(SRC_FILES)
  28. ghdl --synth --std=$(VHD_STD) $(SRC_FILES) -e $(DESIGN_NAME) > $@
  29. $(DESIGN_NAME).json: $(DESIGN_NAME).o
  30. yosys -m ghdl -p 'ghdl --std=$(VHD_STD) --no-formal $(DESIGN_NAME); synth_ice40 -json $@'
  31. clean :
  32. echo "# Cleaning files"
  33. rm -f *.o work*.cf $(DESIGN_NAME).json $(DESIGN_NAME)_synth.vhd