cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

170 lines
5.1 KiB

11 years ago
11 years ago
  1. -- ======================================================================
  2. -- AES encryption/decryption
  3. -- Copyright (C) 2019 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. library osvvm;
  21. use osvvm.RandomPkg.all;
  22. use std.env.all;
  23. use work.aes_pkg.all;
  24. entity tb_aes is
  25. end entity tb_aes;
  26. architecture rtl of tb_aes is
  27. signal s_reset : std_logic := '0';
  28. signal s_clk : std_logic := '0';
  29. signal s_mode : std_logic := '0';
  30. signal s_key : std_logic_vector(0 to 127) := (others => '0');
  31. signal s_datain : std_logic_vector(0 to 127) := (others => '0');
  32. signal s_validin_enc : std_logic := '0';
  33. signal s_acceptout_enc : std_logic;
  34. signal s_dataout_enc : std_logic_vector(0 to 127);
  35. signal s_validout_enc : std_logic;
  36. signal s_acceptin_enc : std_logic := '0';
  37. signal s_validin_dec : std_logic := '0';
  38. signal s_acceptout_dec : std_logic;
  39. signal s_dataout_dec : std_logic_vector(0 to 127);
  40. signal s_validout_dec : std_logic;
  41. signal s_acceptin_dec : std_logic := '0';
  42. procedure cryptData(datain : in std_logic_vector(0 to 127);
  43. key : in std_logic_vector(0 to 127);
  44. mode : in boolean;
  45. dataout : out std_logic_vector(0 to 127);
  46. bytelen : in integer) is
  47. begin
  48. report "VHPIDIRECT cryptData" severity failure;
  49. end procedure;
  50. attribute foreign of cryptData: procedure is "VHPIDIRECT cryptData";
  51. function swap (datain : std_logic_vector(0 to 127)) return std_logic_vector is
  52. variable v_data : std_logic_vector(0 to 127);
  53. begin
  54. for i in 0 to 15 loop
  55. for y in 0 to 7 loop
  56. v_data((i*8)+y) := datain((i*8)+7-y);
  57. end loop;
  58. end loop;
  59. return v_data;
  60. end function;
  61. begin
  62. s_clk <= not(s_clk) after 10 ns;
  63. s_reset <= '1' after 100 ns;
  64. i_aes_enc : aes_enc
  65. port map (
  66. reset_i => s_reset,
  67. clk_i => s_clk,
  68. key_i => s_key,
  69. data_i => s_datain,
  70. valid_i => s_validin_enc,
  71. accept_o => s_acceptout_enc,
  72. data_o => s_dataout_enc,
  73. valid_o => s_validout_enc,
  74. accept_i => s_acceptin_enc
  75. );
  76. i_aes_dec : aes_dec
  77. port map (
  78. reset_i => s_reset,
  79. clk_i => s_clk,
  80. key_i => s_key,
  81. data_i => s_datain,
  82. valid_i => s_validin_dec,
  83. accept_o => s_acceptout_dec,
  84. data_o => s_dataout_dec,
  85. valid_o => s_validout_dec,
  86. accept_i => s_acceptin_dec
  87. );
  88. process is
  89. variable v_key : std_logic_vector(0 to 127);
  90. variable v_datain : std_logic_vector(0 to 127);
  91. variable v_dataout : std_logic_vector(0 to 127);
  92. variable v_random : RandomPType;
  93. begin
  94. v_random.InitSeed(v_random'instance_name);
  95. wait until s_reset = '1';
  96. -- ENCRYPTION TESTs
  97. report "Test encryption";
  98. for i in 0 to 63 loop
  99. wait until rising_edge(s_clk);
  100. s_validin_enc <= '1';
  101. v_key := v_random.RandSlv(128);
  102. v_datain := v_random.RandSlv(128);
  103. s_key <= v_key;
  104. s_datain <= v_datain;
  105. cryptData(swap(v_datain), swap(v_key), true, v_dataout, v_datain'length/8);
  106. wait until s_acceptout_enc = '1' and rising_edge(s_clk);
  107. s_validin_enc <= '0';
  108. wait until s_validout_enc = '1' and rising_edge(s_clk);
  109. s_acceptin_enc <= '1';
  110. assert s_dataout_enc = swap(v_dataout)
  111. report "Encryption error"
  112. severity failure;
  113. wait until rising_edge(s_clk);
  114. s_acceptin_enc <= '0';
  115. end loop;
  116. -- DECRYPTION TESTs
  117. report "Test decryption";
  118. for i in 0 to 63 loop
  119. wait until rising_edge(s_clk);
  120. s_validin_dec <= '1';
  121. v_key := v_random.RandSlv(128);
  122. v_datain := v_random.RandSlv(128);
  123. s_key <= v_key;
  124. s_datain <= v_datain;
  125. cryptData(swap(v_datain), swap(v_key), false, v_dataout, v_datain'length/8);
  126. wait until s_acceptout_dec = '1' and rising_edge(s_clk);
  127. s_validin_dec <= '0';
  128. wait until s_validout_dec = '1' and rising_edge(s_clk);
  129. s_acceptin_dec <= '1';
  130. assert s_dataout_dec = swap(v_dataout)
  131. report "Decryption error"
  132. severity failure;
  133. wait until rising_edge(s_clk);
  134. s_acceptin_dec <= '0';
  135. end loop;
  136. wait for 100 ns;
  137. report "Tests successful";
  138. finish(0);
  139. end process;
  140. end architecture rtl;