cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- CTR-AES
  3. -- Copyright (C) 2020 Torsten Meissner
  4. -------------------------------------------------------------------------
  5. -- This program is free software; you can redistribute it and/or modify
  6. -- it under the terms of the GNU General Public License as published by
  7. -- the Free Software Foundation; either version 2 of the License, or
  8. -- (at your option) any later version.
  9. -- This program is distributed in the hope that it will be useful,
  10. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. -- GNU General Public License for more details.
  13. -- You should have received a copy of the GNU General Public License
  14. -- along with this program; if not, write to the Free Software
  15. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  16. -- ======================================================================
  17. library ieee;
  18. use ieee.std_logic_1164.all;
  19. use ieee.numeric_std.all;
  20. use work.aes_pkg.all;
  21. entity ctraes is
  22. generic (
  23. NONCE_WIDTH : natural range 64 to 96 := 96
  24. );
  25. port (
  26. reset_i : in std_logic; -- low active async reset
  27. clk_i : in std_logic; -- clock
  28. start_i : in std_logic; -- start ctr
  29. nonce_i : in std_logic_vector(0 to NONCE_WIDTH-1); -- nonce
  30. key_i : in std_logic_vector(0 to 127); -- key input
  31. data_i : in std_logic_vector(0 to 127); -- data input
  32. valid_i : in std_logic; -- input key/data valid flag
  33. accept_o : out std_logic; -- input accept
  34. data_o : out std_logic_vector(0 tO 127); -- data output
  35. valid_o : out std_logic; -- output data valid flag
  36. accept_i : in std_logic -- output accept
  37. );
  38. end entity ctraes;
  39. architecture rtl of ctraes is
  40. signal s_aes_datain : std_logic_vector(data_i'range);
  41. signal s_aes_dataout : std_logic_vector(data_o'range);
  42. signal s_aes_key : std_logic_vector(key_i'range);
  43. signal s_key : std_logic_vector(key_i'range);
  44. signal s_nonce : std_logic_vector(nonce_i'range);
  45. signal s_data_in : std_logic_vector(data_i'range);
  46. signal s_counter : unsigned(0 to 127-NONCE_WIDTH);
  47. begin
  48. s_aes_key <= key_i when start_i = '1' else s_key;
  49. s_aes_datain <= nonce_i & (s_counter'range => '0') when start_i = '1' else
  50. s_nonce & std_logic_vector(s_counter);
  51. data_o <= s_aes_dataout xor s_data_in;
  52. inputreg : process (clk_i, reset_i) is
  53. begin
  54. if (reset_i = '0') then
  55. s_key <= (others => '0');
  56. s_nonce <= (others => '0');
  57. s_data_in <= (others => '0');
  58. elsif (rising_edge(clk_i)) then
  59. if (valid_i = '1' and accept_o = '1') then
  60. s_data_in <= data_i;
  61. if (start_i = '1') then
  62. s_key <= key_i;
  63. s_nonce <= nonce_i;
  64. end if;
  65. end if;
  66. end if;
  67. end process inputreg;
  68. counterreg : process (clk_i, reset_i) is
  69. begin
  70. if (reset_i = '0') then
  71. s_counter <= (others => '0');
  72. elsif (rising_edge(clk_i)) then
  73. if (valid_i = '1' and accept_o = '1' and start_i = '1') then
  74. s_counter <= (others => '0');
  75. s_counter(s_counter'high) <= '1';
  76. elsif (valid_i = '1' and accept_o = '1') then
  77. s_counter <= s_counter + 1;
  78. end if;
  79. end if;
  80. end process counterreg;
  81. i_aes_enc : entity work.aes_enc
  82. generic map (
  83. design_type => "ITER"
  84. )
  85. port map (
  86. reset_i => reset_i,
  87. clk_i => clk_i,
  88. key_i => s_aes_key,
  89. data_i => s_aes_datain,
  90. valid_i => valid_i,
  91. accept_o => accept_o,
  92. data_o => s_aes_dataout,
  93. valid_o => valid_o,
  94. accept_i => accept_i
  95. );
  96. end architecture rtl;