cryptography ip-cores in vhdl / verilog
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  1. -- ======================================================================
  2. -- DES encryption/decryption
  3. -- algorithm according to FIPS 46-3 specification
  4. -- Copyright (C) 2007 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. -- Revision 1.0 2007/02/04
  19. -- Initial release
  20. -- Revision 1.1 2007/02/05
  21. -- Corrected error in use of mode register for key calculation
  22. LIBRARY ieee;
  23. USE ieee.std_logic_1164.all;
  24. USE ieee.numeric_std.ALL;
  25. USE work.des_pkg.ALL;
  26. ENTITY des IS
  27. PORT (
  28. clk_i : IN std_logic; -- clock
  29. mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
  30. key_i : IN std_logic_vector(0 TO 63); -- key input
  31. data_i : IN std_logic_vector(0 TO 63); -- data input
  32. valid_i : IN std_logic; -- input key/data valid flag
  33. data_o : OUT std_logic_vector(0 TO 63); -- data output
  34. valid_o : OUT std_logic -- output data valid flag
  35. );
  36. END ENTITY des;
  37. ARCHITECTURE rtl OF des IS
  38. BEGIN
  39. crypt : PROCESS ( clk_i ) IS
  40. -- variables for key calculation
  41. VARIABLE c0 : std_logic_vector(0 TO 27);
  42. VARIABLE c1 : std_logic_vector(0 TO 27);
  43. VARIABLE c2 : std_logic_vector(0 TO 27);
  44. VARIABLE c3 : std_logic_vector(0 TO 27);
  45. VARIABLE c4 : std_logic_vector(0 TO 27);
  46. VARIABLE c5 : std_logic_vector(0 TO 27);
  47. VARIABLE c6 : std_logic_vector(0 TO 27);
  48. VARIABLE c7 : std_logic_vector(0 TO 27);
  49. VARIABLE c8 : std_logic_vector(0 TO 27);
  50. VARIABLE c9 : std_logic_vector(0 TO 27);
  51. VARIABLE c10 : std_logic_vector(0 TO 27);
  52. VARIABLE c11 : std_logic_vector(0 TO 27);
  53. VARIABLE c12 : std_logic_vector(0 TO 27);
  54. VARIABLE c13 : std_logic_vector(0 TO 27);
  55. VARIABLE c14 : std_logic_vector(0 TO 27);
  56. VARIABLE c15 : std_logic_vector(0 TO 27);
  57. VARIABLE c16 : std_logic_vector(0 TO 27);
  58. VARIABLE d0 : std_logic_vector(0 TO 27);
  59. VARIABLE d1 : std_logic_vector(0 TO 27);
  60. VARIABLE d2 : std_logic_vector(0 TO 27);
  61. VARIABLE d3 : std_logic_vector(0 TO 27);
  62. VARIABLE d4 : std_logic_vector(0 TO 27);
  63. VARIABLE d5 : std_logic_vector(0 TO 27);
  64. VARIABLE d6 : std_logic_vector(0 TO 27);
  65. VARIABLE d7 : std_logic_vector(0 TO 27);
  66. VARIABLE d8 : std_logic_vector(0 TO 27);
  67. VARIABLE d9 : std_logic_vector(0 TO 27);
  68. VARIABLE d10 : std_logic_vector(0 TO 27);
  69. VARIABLE d11 : std_logic_vector(0 TO 27);
  70. VARIABLE d12 : std_logic_vector(0 TO 27);
  71. VARIABLE d13 : std_logic_vector(0 TO 27);
  72. VARIABLE d14 : std_logic_vector(0 TO 27);
  73. VARIABLE d15 : std_logic_vector(0 TO 27);
  74. VARIABLE d16 : std_logic_vector(0 TO 27);
  75. -- key variables
  76. VARIABLE key1 : std_logic_vector(0 TO 47);
  77. VARIABLE key2 : std_logic_vector(0 TO 47);
  78. VARIABLE key3 : std_logic_vector(0 TO 47);
  79. VARIABLE key4 : std_logic_vector(0 TO 47);
  80. VARIABLE key5 : std_logic_vector(0 TO 47);
  81. VARIABLE key6 : std_logic_vector(0 TO 47);
  82. VARIABLE key7 : std_logic_vector(0 TO 47);
  83. VARIABLE key8 : std_logic_vector(0 TO 47);
  84. VARIABLE key9 : std_logic_vector(0 TO 47);
  85. VARIABLE key10 : std_logic_vector(0 TO 47);
  86. VARIABLE key11 : std_logic_vector(0 TO 47);
  87. VARIABLE key12 : std_logic_vector(0 TO 47);
  88. VARIABLE key13 : std_logic_vector(0 TO 47);
  89. VARIABLE key14 : std_logic_vector(0 TO 47);
  90. VARIABLE key15 : std_logic_vector(0 TO 47);
  91. VARIABLE key16 : std_logic_vector(0 TO 47);
  92. -- variables for left & right data blocks
  93. VARIABLE l0 : std_logic_vector( 0 TO 31);
  94. VARIABLE l1 : std_logic_vector( 0 TO 31);
  95. VARIABLE l2 : std_logic_vector( 0 TO 31);
  96. VARIABLE l3 : std_logic_vector( 0 TO 31);
  97. VARIABLE l4 : std_logic_vector( 0 TO 31);
  98. VARIABLE l5 : std_logic_vector( 0 TO 31);
  99. VARIABLE l6 : std_logic_vector( 0 TO 31);
  100. VARIABLE l7 : std_logic_vector( 0 TO 31);
  101. VARIABLE l8 : std_logic_vector( 0 TO 31);
  102. VARIABLE l9 : std_logic_vector( 0 TO 31);
  103. VARIABLE l10 : std_logic_vector( 0 TO 31);
  104. VARIABLE l11 : std_logic_vector( 0 TO 31);
  105. VARIABLE l12 : std_logic_vector( 0 TO 31);
  106. VARIABLE l13 : std_logic_vector( 0 TO 31);
  107. VARIABLE l14 : std_logic_vector( 0 TO 31);
  108. VARIABLE l15 : std_logic_vector( 0 TO 31);
  109. VARIABLE l16 : std_logic_vector( 0 TO 31);
  110. VARIABLE r0 : std_logic_vector( 0 TO 31);
  111. VARIABLE r1 : std_logic_vector( 0 TO 31);
  112. VARIABLE r2 : std_logic_vector( 0 TO 31);
  113. VARIABLE r3 : std_logic_vector( 0 TO 31);
  114. VARIABLE r4 : std_logic_vector( 0 TO 31);
  115. VARIABLE r5 : std_logic_vector( 0 TO 31);
  116. VARIABLE r6 : std_logic_vector( 0 TO 31);
  117. VARIABLE r7 : std_logic_vector( 0 TO 31);
  118. VARIABLE r8 : std_logic_vector( 0 TO 31);
  119. VARIABLE r9 : std_logic_vector( 0 TO 31);
  120. VARIABLE r10 : std_logic_vector( 0 TO 31);
  121. VARIABLE r11 : std_logic_vector( 0 TO 31);
  122. VARIABLE r12 : std_logic_vector( 0 TO 31);
  123. VARIABLE r13 : std_logic_vector( 0 TO 31);
  124. VARIABLE r14 : std_logic_vector( 0 TO 31);
  125. VARIABLE r15 : std_logic_vector( 0 TO 31);
  126. VARIABLE r16 : std_logic_vector( 0 TO 31);
  127. -- variables for mode & valid shift registers
  128. VARIABLE mode : std_logic_vector(0 TO 16);
  129. VARIABLE valid : std_logic_vector(0 TO 17);
  130. BEGIN
  131. IF rising_edge( clk_i ) THEN
  132. -- shift registers
  133. valid(1 TO 17) := valid(0 TO 16);
  134. valid(0) := valid_i;
  135. mode(1 TO 16) := mode(0 TO 15);
  136. mode(0) := mode_i;
  137. -- output stage
  138. valid_o <= valid(17);
  139. data_o <= ipn( ( r16 & l16 ) );
  140. -- 16. stage
  141. IF mode(16) = '0' THEN
  142. c16 := c15(1 TO 27) & c15(0);
  143. d16 := d15(1 TO 27) & d15(0);
  144. ELSE
  145. c16 := c15(27) & c15(0 TO 26);
  146. d16 := d15(27) & d15(0 TO 26);
  147. END IF;
  148. key16 := pc2( ( c16 & d16 ) );
  149. l16 := r15;
  150. r16 := l15 xor ( f( r15, key16 ) );
  151. -- 15. stage
  152. IF mode(15) = '0' THEN
  153. c15 := c14(2 TO 27) & c14(0 TO 1);
  154. d15 := d14(2 TO 27) & d14(0 TO 1);
  155. ELSE
  156. c15 := c14(26 TO 27) & c14(0 TO 25);
  157. d15 := d14(26 TO 27) & d14(0 TO 25);
  158. END IF;
  159. key15 := pc2( ( c15 & d15 ) );
  160. l15 := r14;
  161. r15 := l14 xor ( f( r14, key15 ) );
  162. -- 14. stage
  163. IF mode(14) = '0' THEN
  164. c14 := c13(2 TO 27) & c13(0 TO 1);
  165. d14 := d13(2 TO 27) & d13(0 TO 1);
  166. ELSE
  167. c14 := c13(26 TO 27) & c13(0 TO 25);
  168. d14 := d13(26 TO 27) & d13(0 TO 25);
  169. END IF;
  170. key14 := pc2( ( c14 & d14 ) );
  171. l14 := r13;
  172. r14 := l13 xor ( f( r13, key14 ) );
  173. -- 13. stage
  174. IF mode(13) = '0' THEN
  175. c13 := c12(2 TO 27) & c12(0 TO 1);
  176. d13 := d12(2 TO 27) & d12(0 TO 1);
  177. ELSE
  178. c13 := c12(26 TO 27) & c12(0 TO 25);
  179. d13 := d12(26 TO 27) & d12(0 TO 25);
  180. END IF;
  181. key13 := pc2( ( c13 & d13 ) );
  182. l13 := r12;
  183. r13 := l12 xor ( f( r12, key13 ) );
  184. -- 12. stage
  185. IF mode(12) = '0' THEN
  186. c12 := c11(2 TO 27) & c11(0 TO 1);
  187. d12 := d11(2 TO 27) & d11(0 TO 1);
  188. ELSE
  189. c12 := c11(26 TO 27) & c11(0 TO 25);
  190. d12 := d11(26 TO 27) & d11(0 TO 25);
  191. END IF;
  192. key12 := pc2( ( c12 & d12 ) );
  193. l12 := r11;
  194. r12 := l11 xor ( f( r11, key12 ) );
  195. -- 11. stage
  196. IF mode(11) = '0' THEN
  197. c11 := c10(2 TO 27) & c10(0 TO 1);
  198. d11 := d10(2 TO 27) & d10(0 TO 1);
  199. ELSE
  200. c11 := c10(26 TO 27) & c10(0 TO 25);
  201. d11 := d10(26 TO 27) & d10(0 TO 25);
  202. END IF;
  203. key11 := pc2( ( c11 & d11 ) );
  204. l11 := r10;
  205. r11 := l10 xor ( f( r10, key11 ) );
  206. -- 10. stage
  207. IF mode(10) = '0' THEN
  208. c10 := c9(2 TO 27) & c9(0 TO 1);
  209. d10 := d9(2 TO 27) & d9(0 TO 1);
  210. ELSE
  211. c10 := c9(26 TO 27) & c9(0 TO 25);
  212. d10 := d9(26 TO 27) & d9(0 TO 25);
  213. END IF;
  214. key10 := pc2( ( c10 & d10 ) );
  215. l10 := r9;
  216. r10 := l9 xor ( f( r9, key10 ) );
  217. -- 9. stage
  218. IF mode(9) = '0' THEN
  219. c9 := c8(1 TO 27) & c8(0);
  220. d9 := d8(1 TO 27) & d8(0);
  221. ELSE
  222. c9 := c8(27) & c8(0 TO 26);
  223. d9 := d8(27) & d8(0 TO 26);
  224. END IF;
  225. key9 := pc2( ( c9 & d9 ) );
  226. l9 := r8;
  227. r9 := l8 xor ( f( r8, key9 ) );
  228. -- 8. stage
  229. IF mode(8) = '0' THEN
  230. c8 := c7(2 TO 27) & c7(0 TO 1);
  231. d8 := d7(2 TO 27) & d7(0 TO 1);
  232. ELSE
  233. c8 := c7(26 TO 27) & c7(0 TO 25);
  234. d8 := d7(26 TO 27) & d7(0 TO 25);
  235. END IF;
  236. key8 := pc2( ( c8 & d8 ) );
  237. l8 := r7;
  238. r8 := l7 xor ( f( r7, key8 ) );
  239. -- 7. stage
  240. IF mode(7) = '0' THEN
  241. c7 := c6(2 TO 27) & c6(0 TO 1);
  242. d7 := d6(2 TO 27) & d6(0 TO 1);
  243. ELSE
  244. c7 := c6(26 TO 27) & c6(0 TO 25);
  245. d7 := d6(26 TO 27) & d6(0 TO 25);
  246. END IF;
  247. key7 := pc2( ( c7 & d7 ) );
  248. l7 := r6;
  249. r7 := l6 xor ( f( r6, key7 ) );
  250. -- 6. stage
  251. IF mode(6) = '0' THEN
  252. c6 := c5(2 TO 27) & c5(0 TO 1);
  253. d6 := d5(2 TO 27) & d5(0 TO 1);
  254. ELSE
  255. c6 := c5(26 TO 27) & c5(0 TO 25);
  256. d6 := d5(26 TO 27) & d5(0 TO 25);
  257. END IF;
  258. key6 := pc2( ( c6 & d6 ) );
  259. l6 := r5;
  260. r6 := l5 xor ( f( r5, key6 ) );
  261. -- 5. stage
  262. IF mode(5) = '0' THEN
  263. c5 := c4(2 TO 27) & c4(0 TO 1);
  264. d5 := d4(2 TO 27) & d4(0 TO 1);
  265. ELSE
  266. c5 := c4(26 TO 27) & c4(0 TO 25);
  267. d5 := d4(26 TO 27) & d4(0 TO 25);
  268. END IF;
  269. key5 := pc2( ( c5 & d5 ) );
  270. l5 := r4;
  271. r5 := l4 xor ( f( r4, key5 ) );
  272. -- 4. stage
  273. IF mode(4) = '0' THEN
  274. c4 := c3(2 TO 27) & c3(0 TO 1);
  275. d4 := d3(2 TO 27) & d3(0 TO 1);
  276. ELSE
  277. c4 := c3(26 TO 27) & c3(0 TO 25);
  278. d4 := d3(26 TO 27) & d3(0 TO 25);
  279. END IF;
  280. key4 := pc2( ( c4 & d4 ) );
  281. l4 := r3;
  282. r4 := l3 xor ( f( r3, key4 ) );
  283. -- 3. stage
  284. IF mode(3) = '0' THEN
  285. c3 := c2(2 TO 27) & c2(0 TO 1);
  286. d3 := d2(2 TO 27) & d2(0 TO 1);
  287. ELSE
  288. c3 := c2(26 TO 27) & c2(0 TO 25);
  289. d3 := d2(26 TO 27) & d2(0 TO 25);
  290. END IF;
  291. key3 := pc2( ( c3 & d3 ) );
  292. l3 := r2;
  293. r3 := l2 xor ( f( r2, key3 ) );
  294. -- 2. stage
  295. IF mode(2) = '0' THEN
  296. c2 := c1(1 TO 27) & c1(0);
  297. d2 := d1(1 TO 27) & d1(0);
  298. ELSE
  299. c2 := c1(27) & c1(0 TO 26);
  300. d2 := d1(27) & d1(0 TO 26);
  301. END IF;
  302. key2 := pc2( ( c2 & d2 ) );
  303. l2 := r1;
  304. r2 := l1 xor ( f( r1, key2 ) );
  305. -- 1. stage
  306. IF mode(1) = '0' THEN
  307. c1 := c0(1 TO 27) & c0(0);
  308. d1 := d0(1 TO 27) & d0(0);
  309. ELSE
  310. c1 := c0;
  311. d1 := d0;
  312. END IF;
  313. key1 := pc2( ( c1 & d1 ) );
  314. l1 := r0;
  315. r1 := l0 xor ( f( r0, key1 ) );
  316. -- input stage
  317. l0 := ip( data_i )(0 TO 31);
  318. r0 := ip( data_i )(32 TO 63);
  319. c0 := pc1_c( key_i );
  320. d0 := pc1_d( key_i );
  321. END IF;
  322. END PROCESS crypt;
  323. END ARCHITECTURE rtl;