added timescale directive and set it to 1 ns/1 ps

des/sim/verilog/tb_des.v

@@ -18,6 +18,8 @@
 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 // ======================================================================
 
+`timescale 1ns/1ps
+
 
 module tb_des;