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add acceptin & acceptout ports

master
T. Meissner 11 years ago
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b9efb85f01
commit
cb14f089b9
1 changed files with 2 additions and 0 deletions
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  1. +2
    -0
      des/sim/verilog/tb_des.tcl

+ 2
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des/sim/verilog/tb_des.tcl View File

@ -2,9 +2,11 @@ set signals [list]
lappend signals "tb_des.reset"
lappend signals "tb_des.clk"
lappend signals "tb_des.validin"
lappend signals "tb_des.acceptout"
lappend signals "tb_des.mode"
lappend signals "tb_des.key"
lappend signals "tb_des.datain"
lappend signals "tb_des.validout"
lappend signals "tb_des.acceptin"
lappend signals "tb_des.dataout"
set num_added [ gtkwave::addSignalsFromList $signals ]

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