CTR-AES: Fix counter incr & init; add 1st simple testbench

* Fix counter init & increase enable to prevent aes_enc PSL assume error
* Add CTR-AES testbench, at the moment without data checks

.github/test.sh

@@ -12,6 +12,6 @@ run_sim() {
   echo '::endgroup::'
 }
 
-for item in aes cbcdes cbcmac_des cbctdes des tdes; do
+for item in aes cbcdes cbcmac_des cbctdes ctraes des tdes; do
   run_sim $item
 done

ctraes/rtl/vhdl/ctraes.vhd

@@ -93,8 +93,9 @@ begin
       s_counter <= (others => '0');
     elsif (rising_edge(clk_i)) then
       if (valid_i = '1' and accept_o = '1' and start_i = '1') then
-        s_counter <= (others => '0');
-      elsif (valid_o = '1' and accept_i = '1') then
+        s_counter   <= (others => '0');
+        s_counter(s_counter'high) <= '1';
+      elsif (valid_i = '1' and accept_o = '1') then
         s_counter <= s_counter + 1;
       end if;
     end if;

ctraes/sim/vhdl/Makefile

@@ -0,0 +1,96 @@
+# ======================================================================
+# AES encryption/decryption
+# Copyright (C) 2019 Torsten Meissner
+#-----------------------------------------------------------------------
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+# ======================================================================
+
+
+.SECONDARY:
+
+
+DESIGN_NAME := ctraes
+RTL_SRC := \
+  ../../../aes/rtl/vhdl/aes_pkg.vhd \
+  ../../../aes/rtl/vhdl/aes_enc.vhd \
+  ../../rtl/vhdl/$(DESIGN_NAME).vhd
+
+
+SIM_SRC   := tb_$(DESIGN_NAME).vhd
+
+
+OSVVM_DIR := ../../../lib/osvvm
+OSVVM_SRC := \
+  $(OSVVM_DIR)/NamePkg.vhd  \
+  $(OSVVM_DIR)/OsvvmGlobalPkg.vhd  \
+  $(OSVVM_DIR)/VendorCovApiPkg.vhd  \
+  $(OSVVM_DIR)/TranscriptPkg.vhd  \
+  $(OSVVM_DIR)/TextUtilPkg.vhd  \
+  $(OSVVM_DIR)/AlertLogPkg.vhd  \
+  $(OSVVM_DIR)/MessagePkg.vhd  \
+  $(OSVVM_DIR)/SortListPkg_int.vhd  \
+  $(OSVVM_DIR)/RandomBasePkg.vhd  \
+  $(OSVVM_DIR)/RandomPkg.vhd  \
+  $(OSVVM_DIR)/CoveragePkg.vhd  \
+  $(OSVVM_DIR)/MemoryPkg.vhd  \
+  $(OSVVM_DIR)/ScoreboardGenericPkg.vhd  \
+  $(OSVVM_DIR)/ScoreboardPkg_slv.vhd  \
+  $(OSVVM_DIR)/ScoreboardPkg_int.vhd  \
+  $(OSVVM_DIR)/ResolutionPkg.vhd  \
+  $(OSVVM_DIR)/TbUtilPkg.vhd  \
+  $(OSVVM_DIR)/OsvvmContext.vhd
+
+VHD_STD := 08
+
+
+.PHONY: sim
+sim: tb_$(DESIGN_NAME).ghw
+
+
+.PHONY: compile
+compile: tb_$(DESIGN_NAME)
+
+
+osvvm work:
+	mkdir $@
+
+
+osvvm/OsvvmContext.o: $(OSVVM_SRC) | osvvm
+	@echo "Analyze OSVVM library ..."
+	ghdl -a --std=$(VHD_STD) -Wno-hide --work=osvvm --workdir=osvvm $(OSVVM_SRC)
+
+
+tb_$(DESIGN_NAME): ${RTL_SRC} ${SIM_SRC} osvvm/OsvvmContext.o | work
+	@echo "Analyze testbench & design ..."
+	ghdl -a --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm ${RTL_SRC} ${SIM_SRC}
+	@echo "Elaborate testbench & design ..."
+	ghdl -e --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm $@
+
+
+tb_$(DESIGN_NAME).ghw: tb_$(DESIGN_NAME)
+	@echo "Run testbench ..."
+	ghdl -r $(basename $@) --wave=$@ --assert-level=error --psl-report=$(basename $@)_psl_report.json
+
+
+.PHONY: wave
+wave: tb_$(DESIGN_NAME).ghw
+	@echo "Run GTKwave ..."
+	gtkwave -S tb_$(DESIGN_NAME).tcl tb_$(DESIGN_NAME).ghw
+
+
+.PHONY: clean
+clean:
+	@echo "Cleaning simulation files ..."
+	rm -rf tb_$(DESIGN_NAME) tb_$(DESIGN_NAME).ghw *.o *.json work/ osvvm/

ctraes/sim/vhdl/tb_ctraes.tcl

@@ -0,0 +1,13 @@
+set signals [list]
+lappend signals "top.tb_ctraes.s_reset"
+lappend signals "top.tb_ctraes.s_clk"
+lappend signals "top.tb_ctraes.s_validin"
+lappend signals "top.tb_ctraes.s_acceptin"
+lappend signals "top.tb_ctraes.s_start"
+lappend signals "top.tb_ctraes.s_key"
+lappend signals "top.tb_ctraes.s_nonce"
+lappend signals "top.tb_ctraes.s_datain"
+lappend signals "top.tb_ctraes.s_validout"
+lappend signals "top.tb_ctraes.s_acceptout"
+lappend signals "top.tb_ctraes.s_dataout"
+set num_added [ gtkwave::addSignalsFromList $signals ]

ctraes/sim/vhdl/tb_ctraes.vhd

@@ -0,0 +1,125 @@
+-- ======================================================================
+-- AES Counter mode testbench
+-- Copyright (C) 2020 Torsten Meissner
+-------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2 of the License, or
+-- (at your option) any later version.
+
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+-- ======================================================================
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library osvvm;
+  use osvvm.RandomPkg.all;
+
+use std.env.all;
+
+
+entity tb_ctraes is
+end entity tb_ctraes;
+
+
+architecture sim of tb_ctraes is
+
+
+  constant C_NONCE_WIDTH : natural range 64 to 96 := 96;
+
+
+  signal s_reset    : std_logic := '0';
+  signal s_clk      : std_logic := '0';
+
+  signal s_start    : std_logic := '0';
+  signal s_nonce    : std_logic_vector(0 to C_NONCE_WIDTH-1) := (others => '0');
+  signal s_key      : std_logic_vector(0 to 127) := (others => '0');
+  signal s_datain   : std_logic_vector(0 to 127) := (others => '0');
+  signal s_validin  : std_logic := '0';
+  signal s_acceptin : std_logic;
+
+  signal s_dataout   : std_logic_vector(0 to 127);
+  signal s_validout  : std_logic := '0';
+  signal s_acceptout : std_logic := '0';
+
+
+begin
+
+
+  i_ctraes : entity work.ctraes
+  generic map (
+    NONCE_WIDTH => C_NONCE_WIDTH
+  )
+  port map (
+    reset_i  => s_reset,
+    clk_i    => s_clk,
+    start_i  => s_start,
+    nonce_i  => s_nonce,
+    key_i    => s_key,
+    data_i   => s_datain,
+    valid_i  => s_validin,
+    accept_o => s_acceptin,
+    data_o   => s_dataout,
+    valid_o  => s_validout,
+    accept_i => s_acceptout
+  );
+
+
+  s_clk   <= not(s_clk) after 10 ns;
+  s_reset <= '1' after 100 ns;
+
+
+  process is
+    variable v_random  : RandomPType;
+  begin
+    v_random.InitSeed(v_random'instance_name);
+    wait until s_reset = '1' and rising_edge(s_clk);
+    -- ENCRYPTION TESTs
+    report "Test encryption";
+    for i in 0 to 31 loop
+      if (i = 0) then
+        s_start <= '1';
+        s_nonce <= v_random.RandSlv(s_nonce'length);
+      else
+        s_start <= '0';
+      end if;
+      s_validin <= '1';
+      s_key     <= v_random.RandSlv(128);
+      s_datain  <= v_random.RandSlv(128);
+      report "Test #" & to_string(i);
+      wait until s_acceptin = '1' and rising_edge(s_clk);
+      s_validin <= '0';
+    end loop;
+    -- Watchdog
+    wait for 1 us;
+    report "Watchdog error"
+      severity failure;
+  end process;
+
+
+  process is
+  begin
+    s_acceptout <= '0';
+    for i in 0 to 31 loop
+    wait until s_validout = '1' and rising_edge(s_clk);
+      s_acceptout <= '1';
+      wait until rising_edge(s_clk);
+      s_acceptout <= '0';
+    end loop;
+    report "Tests finished";
+    wait for 100 ns;
+    finish(0);
+  end process;
+
+
+end architecture sim;