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changed reset & clk timing according to vhdl testbench

master
T. Meissner 11 years ago
parent
commit
f8226943a3
1 changed files with 3 additions and 3 deletions
  1. +3
    -3
      cbctdes/sim/verilog/tb_cbctdes.v

+ 3
- 3
cbctdes/sim/verilog/tb_cbctdes.v View File

@ -63,11 +63,11 @@ module tb_cbctdes;
initial begin
reset = 1;
#1 reset = 0;
#20 reset = 1;
#100 reset = 1;
end
// generate clock with 100 mhz
always #5 clk = !clk;
// generate clock with 50 mhz
always #10 clk = !clk;
// init the register values


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