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cryptocores
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7 Commits (553e105986b6a97c79a77f71d0bf15d026e53371)

Author SHA1 Message Date
  T. Meissner c42beff5b8 moved vhdl design files in directory 'vhdl' 12 years ago
  T. Meissner ab47fd3a54 import verilog des design files from des project 12 years ago
  T. Meissner 6356f624af moved vhdl design files in directory 'vhdl' 12 years ago
  Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
  Torsten Meissner 5f440e10ad Revision 0.2 2011/10/06 13 years ago
  Torsten Meissner b9ed938d6d register mode_i and iv_i only if start_i is high 13 years ago
  Torsten Meissner 5c4b112411 Initial Release of CBC-DES 13 years ago