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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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194
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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0a7ed338d6
master
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cryptocores
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des
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sim
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verilog
History
T. Meissner
8f575798ea
add .PHONY to clean target
10 years ago
..
data_input.txt
added test data for decryption test cases
12 years ago
data_output.txt
added test data for decryption test cases
12 years ago
key_input.txt
added test data for decryption test cases
12 years ago
makefile
add .PHONY to clean target
10 years ago
tb_des.tcl
add acceptin & acceptout ports
10 years ago
tb_des.v
add support for ITER & PIPE variations of DES verilog implementation
10 years ago