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93 lines
2.3 KiB
93 lines
2.3 KiB
// ======================================================================
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// CBC-MAC-DES
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// Copyright (C) 2015 Torsten Meissner
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//-----------------------------------------------------------------------
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2 of the License, or
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// (at your option) any later version.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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// ======================================================================
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`timescale 1ns/1ps
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`define ITER
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module cbcmac_des (
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input reset_i,
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input clk_i,
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input start_i,
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input [0:63] key_i,
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input [0:63] data_i,
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input valid_i,
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output accept_o,
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output [0:63] data_o,
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output valid_o,
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input accept_i
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);
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// CBCMAC must have fix IV for security reasons
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reg [0:63] iv = 0;
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reg [0:63] key;
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wire [0:63] des_key;
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wire [0:63] des_datain;
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reg [0:63] des_dataout_d;
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assign des_datain = start_i ? iv ^ data_i : des_dataout_d ^ data_i;
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assign des_key = start_i ? key_i : key;
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// input register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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key <= 0;
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end
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else begin
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if (valid_i && accept_o && start_i) begin
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key <= key_i;
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end
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end
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end
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// output register
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always @(posedge clk_i, negedge reset_i) begin
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if (~reset_i) begin
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des_dataout_d <= 0;
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end
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else begin
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if (valid_o) begin
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des_dataout_d <= data_o;
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end
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end
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end
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// des instance
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des i_des (
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.reset_i(reset_i),
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.clk_i(clk_i),
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.mode_i(1'b0),
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.key_i(des_key),
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.data_i(des_datain),
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.valid_i(valid_i),
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.accept_o(accept_o),
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.data_o(data_o),
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.valid_o(valid_o),
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.accept_i(accept_i)
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);
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endmodule
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