cryptography ip-cores in vhdl / verilog
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umarcor 17ce27949f ci: rename 'test' workflow to 'Simulation' 10 months ago
.github ci: rename 'test' workflow to 'Simulation' 10 months ago
aes aes: fix build arg order 10 months ago
cbcdes Update CBCDES unit and tests 1 year ago
cbcmac_aes Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 1 year ago
cbcmac_des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 1 year ago
cbctdes Add Makefile for synthesis of CBCTDES 10 months ago
ctraes CTR-AES: Fix counter incr & init; add 1st simple testbench 10 months ago
des Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 1 year ago
lib Add OSVVM as submodule 1 year ago
tdes Minor update to TDES sim makefile and testbench 10 months ago
.gitignore added ignore file 8 years ago
.gitmodules Add OSVVM as submodule 1 year ago
LICENSE.textile added GPLv2 license file 7 years ago
README.md Add GHA badge 10 months ago

README.md

simulation

cryptocores

Cryptography IP-cores & tests written in VHDL / Verilog

The components in this repository are not intended as productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.