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cryptography ip-cores in vhdl / verilog
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cryptocores/tdes/sim/verilog
T. Meissner 5c74abc86f added wait for disactivated reset before running testcases 10 years ago
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makefile initial commit of verilog simulation environment for tdes core 11 years ago
tb_tdes.tcl initial commit of verilog simulation environment for tdes core 11 years ago
tb_tdes.v added wait for disactivated reset before running testcases 10 years ago
test_data.txt initial commit of verilog simulation environment for tdes core 11 years ago