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159 lines
4.5 KiB
159 lines
4.5 KiB
-- ======================================================================
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-- AES encryption/decryption
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-- Copyright (C) 2019 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.aes_pkg.all;
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entity aes_enc is
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generic (
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design_type : string := "ITER"
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);
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port (
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reset_i : in std_logic; -- async reset
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clk_i : in std_logic; -- clock
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key_i : in std_logic_vector(0 to 127); -- key input
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data_i : in std_logic_vector(0 to 127); -- data input
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valid_i : in std_logic; -- input key/data valid flag
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accept_o : out std_logic;
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data_o : out std_logic_vector(0 to 127); -- data output
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valid_o : out std_logic; -- output data valid flag
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accept_i : in std_logic
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);
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end entity aes_enc;
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architecture rtl of aes_enc is
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begin
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IterG : if design_type = "ITER" generate
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signal s_round : t_enc_rounds;
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begin
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CryptP : process (reset_i, clk_i) is
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variable v_state : t_datatable2d;
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variable v_key : t_key;
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begin
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if (reset_i = '0') then
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v_state := (others => (others => (others => '0')));
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v_key := (others => (others => '0'));
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s_round <= 0;
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accept_o <= '0';
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data_o <= (others => '0');
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valid_o <= '0';
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elsif (rising_edge(clk_i)) then
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case s_round is
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when 0 =>
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accept_o <= '1';
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if (accept_o = '1' and valid_i = '1') then
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accept_o <= '0';
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v_state := set_state(data_i);
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v_key := set_key(key_i);
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s_round <= s_round + 1;
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end if;
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when 1 =>
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v_state := addroundkey(v_state, v_key);
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v_key := key_round(v_key, s_round-1);
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s_round <= s_round + 1;
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when t_enc_rounds'high-1 =>
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v_state := subbytes(v_state);
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v_state := shiftrow(v_state);
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v_state := addroundkey(v_state, v_key);
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s_round <= s_round + 1;
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-- set data & valid to save one cycle
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valid_o <= '1';
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data_o <= get_state(v_state);
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when t_enc_rounds'high =>
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if (valid_o = '1' and accept_i = '1') then
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valid_o <= '0';
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data_o <= (others => '0');
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s_round <= 0;
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-- Set accept to save one cycle
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accept_o <= '1';
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end if;
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when others =>
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v_state := subbytes(v_state);
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v_state := shiftrow(v_state);
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v_state := mixcolumns(v_state);
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v_state := addroundkey(v_state, v_key);
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v_key := key_round(v_key, s_round-1);
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s_round <= s_round + 1;
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end case;
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end if;
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end process CryptP;
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-- synthesis off
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verification : block is
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signal s_data : std_logic_vector(0 to 127);
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begin
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s_data <= data_o when rising_edge(clk_i) else
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128x"0" when reset_i = '0';
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default clock is rising_edge(Clk_i);
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cover {accept_o};
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assert always (accept_o -> s_round = 0);
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cover {valid_i and accept_o};
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assert always (valid_i and accept_o -> next not accept_o);
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cover {valid_o};
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assert always (valid_o -> s_round = t_enc_rounds'high);
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cover {valid_o and accept_i};
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assert always (valid_o and accept_i -> next not valid_o);
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cover {valid_o and not accept_i};
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assert always (valid_o and not accept_i -> next valid_o);
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assert always (valid_o and not accept_i -> next data_o = s_data);
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end block verification;
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-- synthesis on
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end generate IterG;
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end architecture rtl;
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