tmeissner
/
cryptocores
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
191 Commits
1 Branch
1.7 MiB
 
 
 
 
 
Tree: 303bda25e4
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '303bda25e4'
${ noResults }
 ZIP  TAR.GZ
T. Meissner 303bda25e4 Add CTR-AES VHDL design 4 years ago
aes Refactoring; remove unused functions 4 years ago
cbcdes moved array type definitions out of functions to head of package, instances now also in package head and are constants 11 years ago
cbcmac_aes/rtl/vhdl Add CBCMAC-AES VHDL design 4 years ago
cbcmac_des merge last changes from amc mini repo 10 years ago
cbctdes removed internal synced copy of reset_i; set ready to high in reset 11 years ago
ctraes/rtl/vhdl Add CTR-AES VHDL design 4 years ago
des merge last changes from amc mini repo 10 years ago
tdes added removing of tb_tdes binary and *.o files in clean target 11 years ago
.gitignore added ignore file 11 years ago
LICENSE.textile added GPLv2 license file 10 years ago
README.md Created Readme.md file 8 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.