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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
78
Commits
1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
Tree:
3399288adc
cryptocores
/
des
History
Torsten Meissner
3399288adc
change lib path for simulation
13 years ago
..
rtl
change lib path for simulation
13 years ago
sim
moved vhdl testbench files into separate directory vhdl under sim
13 years ago