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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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40
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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Torsten Meissner
36aeb55a1c
new tcl-file to control gtkwave
13 years ago
aes
added array constants for forward & reverse s-boxes
13 years ago
cbcdes
added async reset to des-module to avoid simulation warnings and unititialized ports
13 years ago
cbctdes
initial release of tdes in cbc mode
13 years ago
des
new tcl-file to control gtkwave
13 years ago
tdes
added async reset to des-module to avoid simulation warnings and unititialized ports
13 years ago