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cryptography ip-cores in vhdl / verilog
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Tree: 4b8ab0d0cc
cryptocores/tdes
Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 14 years ago
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rtl added async reset to des-module to avoid simulation warnings and unititialized ports 14 years ago
sim minor updates 14 years ago