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cryptography ip-cores in vhdl / verilog
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Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
cbcdes added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
des added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago
tdes added async reset to des-module to avoid simulation warnings and unititialized ports 13 years ago