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cryptography ip-cores in vhdl / verilog
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cryptocores/ctraes
T. Meissner 4c3aa07711 Update CTR-AES testbench to use openSSL as reference, unpolished 4 years ago
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rtl/vhdl CTR-AES: Fix counter incr & init; add 1st simple testbench 4 years ago
sim/vhdl Update CTR-AES testbench to use openSSL as reference, unpolished 4 years ago
syn/vhdl Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring 4 years ago