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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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202
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1
Branch
1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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5640e7884b
master
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cryptocores
/
cbcmac_des
/
sim
/
verilog
History
T. Meissner
313a08b6f3
add verilog simulation environment for cbcmac-des
10 years ago
..
data_input.txt
add verilog simulation environment for cbcmac-des
10 years ago
data_output.txt
add verilog simulation environment for cbcmac-des
10 years ago
makefile
add verilog simulation environment for cbcmac-des
10 years ago
tb_cbcmac_des.tcl
add verilog simulation environment for cbcmac-des
10 years ago
tb_cbcmac_des.v
add verilog simulation environment for cbcmac-des
10 years ago