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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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81
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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History
Torsten Meissner
5fde3ac4a7
added outdex to wave view
13 years ago
..
rtl
change lib path for simulation
13 years ago
sim
added outdex to wave view
13 years ago